MPC8280 datasheet(1257/1386 Pages) FREESCALE

1257 / 1386 page

Fast Ethernet Controller

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

36-23

Figure 36-8 shows interrupts that can be generated in the Ethernet protocol.

Figure 36-8. Ethernet Interrupt Events Example

NOTE

The FCC status register is not valid for the Ethernet protocol. The current

state of the MII signals can be read through the parallel ports.

36.19 Ethernet RxBDs

The Ethernet controller uses the RxBD to report information about the received data for each buffer.

Figure 36-9 shows the FCC Ethernet RxBD format.

RXB

Line Idle

Stored in Rx Buffer

RXD

RX_DV

Frame

Received in Ethernet

Time

Line Idle

TXD

TX_EN

Frame

Transmitted by Ethernet

COL

TXB, GRA

TXB

Line Idle

Stored in Tx Buffer

Notes:

Ethernet FCCE

Events

1. RXB event assumes receive buffers are 64 bytes each.

2. The RXF interrupt may occur later than RX_DV due to receive FIFO latency.

Notes:

Ethernet FCCE

Events

1. TXB events assume the frame required two transmit buffers.

2. The GRA event assumes a graceful stop transmit command was issued during frame transmission.

PSFD DA SA

RXF

T/L

PSFD DA SA

T/L

Legend:

P = Preamble, SFD = Start frame delimiter, DA and SA = Destination/Source address,

T/L = Type/Length, D = Data, CR = CRC bytes

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