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MPC8280 bảng dữ liệu(PDF) 767 Page - Freescale Semiconductor, Inc

tên linh kiện MPC8280
Giải thích chi tiết về linh kiện  PowerQUICC??II Family Reference Manual
PDF  1386 Pages
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nhà sản xuất  FREESCALE [Freescale Semiconductor, Inc]
Trang chủ  http://www.freescale.com
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MPC8280 bảng dữ liệu(HTML) 767 Page - Freescale Semiconductor, Inc

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SCC BISYNC Mode
MPC8280 PowerQUICC II Family Reference Manual, Rev. 1
Freescale Semiconductor
23-13
Data length and buffer pointer fields are described in Section 20.2, “SCC Buffer Descriptors (BDs).” Data
length represents the number of octets the CP writes into this buffer, including the BCS. For BISYNC
mode, clear these bits. It is incremented each time a received character is written to the buffer.
2
W
Wrap (last BD in table).
0 Not the last BD in the table.
1 Last BD in the table. After this buffer is used, the CP receives incoming data into the first BD that
RBASE points to. The number of BDs in this table is determined by the W bit and by overall space
constraints of the dual-port RAM.
3
I
Interrupt.
0 No interrupt is generated after this buffer is used.
1 SCCE[RXB] is set when the controller closes this buffer, which can cause an interrupt if it is
enabled.
4
C
Control Character. The last byte in the buffer is a user-defined control character.
0 The last byte of this buffer does not contain a control character.
1 The last byte of this buffer contains a control character.
5
B
BCS received. The last bytes in the buffer contain the received BCS.
0 This buffer does not contain the BCS.
1 This buffer contains the BCS. A control character may also reside one byte prior to this BCS.
6
CM
Continuous mode.
0 Normal operation.
1 The CP does not clear E after this BD is closed; the buffer is overwritten when the CP accesses
this BD next. However, E is cleared if an error occurs during reception, regardless of how CM is
set.
7
—
Reserved, should be cleared.
8
DE
DPLL error. Set when a DPLL error occurs during reception. In decoding modes where a transition
is should occur every bit, the DPLL error is set when a transition is missing.
9–10
—
Reserved, should be cleared.
11
DL
DLE follow character error. While in transparent mode, a DLE character was received, and the next
character was not DLE, SYNC, or a valid entry in the control characters table.
12
PR
Parity error. Set when a character with parity error is received. Upon a parity error, the buffer is
closed; thus, the corrupted character is the last byte of the buffer. A new Rx buffer receives
subsequent data.
13
CR
BCS error. Updated every time a byte is written to the buffer. The CR bit includes the calculation for
the current byte. By clearing PSMR[RCBS] within eight serial clocks, the user can exclude the
current character from the message BCS calculation. The data length field may be read to
determine the current character’s position.
14
OV
Overrun. Set when a receiver overrun occurs during frame reception.
15
CD
Carrier detect lost. Indicates when the carrier detect signal, CD, is negated during frame reception.
Table 23-11. SCC BISYNC RxBD Status and Control Field Descriptions (continued)
Bits
Name
Description



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