MPC8280 datasheet(628/1386 Pages) FREESCALE

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CPM Multiplexing

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

16-16

Freescale Semiconductor

16.4.5

CMX SCC Clock Route Register (CMXSCR)

The CMX SCC clock route register (CMXSCR), seen in Figure 16-11, defines the connection of the SCCs

to the TSA and to the clock sources from the bank of clocks. This register also enables the use of the

external grant pin.

Table 16-6 describes CMXSCR fields.

21–23

TF3CS

Transmit FCC3 clock source (NMSI mode). Ignored if FCC3 is connected to the TSA (FC3 = 1).

000 FCC3 transmit clock is BRG5.

001 FCC3 transmit clock is BRG6.

010 FCC3 transmit clock is BRG7.

011 FCC3 transmit clock is BRG8.

100 FCC3 transmit clock is CLK13.

101 FCC3 transmit clock is CLK14.

110 FCC3 transmit clock is CLK15.

111 FCC3 transmit clock is CLK16.

24–31

—

Reserved, should be cleared

Field GR1

SC1

RS1CS

TS1CS

GR2

SC2

RS2CS

TS2CS

Reset

0000_0000_0000_0000

R/W

Addr

0x11B08

Field GR3

SC3

RS3CS

TS3CS

GR4

SC4

RS4CS

TS4CS

Reset

0000_0000_0000_0000

R/W

Addr

0x11B0A

Figure 16-11. CMX SCC Clock Route Register (CMXSCR)

Table 16-6. CMXSCR Field Descriptions

Bits

Name

Description

GR1

Grant support of SCC1

0 SCC1 transmitter does not support the grant mechanism. The grant is always asserted internally.

1 SCC1 transmitter supports the grant mechanism as determined by the GMx bit of a serial device

channel.

SC1

SCC1 connection

0 SCC1 is not connected to the TSA and is either connected directly to the NMSIx pins or is not

used. The choice of general-purpose I/O port pins versus SCCn pins is made in the parallel I/O

control register.

1 SCC1 is connected to TSA of the SIs. The NMSIx pins are available for other purposes.

Table 16-5. CMXFCR Field Descriptions (continued)

Bits

Name

Description

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