MPC8280 datasheet(503/1386 Pages) FREESCALE

503 / 1386 page

Memory Controller

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

11-83

After timings are created, programming the UPM continues with translating these timings into tables

representing the RAM array contents for each possible cycle. When a table is completed, the global

parameters of the UPM must be defined for handling the disable timer (precharge) and the refresh timer

relative to Figure 11-67. Table 11-42 shows settings of different fields.

The OR and BR of the specific bank must be initialized according to the address mapping of the DRAM

device used. The MS field should indicate the specific UPM selected to handle the cycle. The RAM array

of the UPM can than be written through use of the MxMR[OP] = 11. Figure 11-56 shows the first locations

addressed by the UPM, according to the different services required by the DRAM.

Table 11-42. UPMs Attributes Example

Explanation

Field

Value

Machine select UPMA

x[MS]

0b100

Port size 64-bit

x[PS]

0b00

No write protect (R/W)

x[WP]

0b0

Refresh timer value (1024 refresh cycles)

PURT[PURT]

0x0C

Refresh timer enable

xMR[RFEN]

0b1

Address multiplex size

xMR[AMx]

0b010

Disable timer period

xMR[DSx]

0b01

Select between GPL4 and UPMWAIT = GPL4 data sample at clock rising edge

xMR[GPL_x4DIS]

0b0

Burst inhibit device

x[BI]

0b0

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