MPC8280 datasheet(501/1386 Pages) FREESCALE

501 / 1386 page

Memory Controller

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

11-81

This means that the address bus should be partitioned as shown in Table 11-39.

From the device perspective, during RAS assertion, its address port should look like Table 11-40:

Table 11-38 indicates that to multiplex A[8–19] over A[17–28], choose AMx= 001.

Table 11-41 shows the register configuration. Not shown are PURT and MPTPR, which should be

programmed according to the device refresh requirements.

11.6.6

Differences Between the MPC8xx UPM and MPC82xx UPM

Users familiar with the MPC8xx UPM should read this section first.

Below is a list of the major differences between the MPC8xx devices and the MPC82xx:

•

First cycle timing transferred to the UPM array—In the MPC8xx’s UPM, the first cycle value of

some of the signals is determined from ORx[SAM,G5LA,G5LS]. This is eliminated in the

MPC8280. All signals are controlled only by the pattern written to the array.

•

Timing of GPL[0–5]—In the MPC8xx’s UPM, the GPL lines could change on the positive edge of

T2 or T3. In the MPC8280 these signals can change in the positive edge of T1 or T3 to allow

connection to high-speed synchronous devices such as burst SRAM.

•

UPM controlled signals negated at end of an access—In the MPC8xx’s UPM, if the user did not

negate the UPM signals at end of an access, those signals kept their previous value. In the

PowerQUICC II, all UPM signals are negated (CS,BS,GPL[0:4] driven to logic 1 and GPL5 driven

Table 11-39. 60x Address Bus Partition

A[0–7]

A[8–19]

A[20–28]

A[29–31]

msb of start address

Row

Column

lsb

Table 11-40. DRAM Device Address Port during an ACTIVATE command

“A[0–16]”

A[17–28]

A[29–31]

—

Row (A[8–19])

n.c.

Table 11-41. Register Settings

Settings

BRx

BA msb of base address

PS 00 = 64-bit port size

DECC00

WP0

MS 100 = UPMA

EMEMC0

ATOM00

DR 0

AM 1111_1111_0000_0000_0 = 16 Mbyte

BI 0

EHTR0

xMR

BSEL0 = 60x bus

RFEN1

OP 00

AM 001

DSAAs needed

G0CLAN/A

GPL_A4DIS0

RLFAAs needed

WLFAAs needed

TLFAAs needed

MADN/A

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