MPC8280 datasheet(418/1386 Pages) FREESCALE

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Clocks and Power Control

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

10-8

Freescale Semiconductor

Note: At PCI Agent mode, when PCI_MODCK = 0, the ratio of CPM_CLK/PCI_CLK should be calculated from PLLMF as follows:

CPM_CLK / PCI_CLK = (PLLMF + 1) / 2.

At PCI Agent mode, when PCI_MODCK = 1, the ratio of CPM_CLK/PCI_CLK should be calculated from PLLMF as follows:

PLLMF = 3 > CPM_CLK / PCI_CLK = 4

PLLMF = 5 > CPM_CLK / PCI_CLK = 6

PLLMF = 7 > CPM_CLK / PCI_CLK = 8

PLLMF = 9 > CPM_CLK / PCI_CLK = 5

PLLMF = B > CPM_CLK / PCI_CLK = 6

10.5.1

Core PLL Configurations

Table 10-4 shows SCMR[CORECNF] bit values and translations to the core PLL mode.

16–27

—

Reserved

28–31

PLLMF

Config pins

Unaffected

PLL multiplication factor. PLLMF controls the value of the divider in

the PLL feedback loop.

Note: The definition of PLLMF depends on the clock mode2:

• Local bus and PCI host: PLLMF = 2(CPM_CLK/CLKIN) – 1

• PCI agent: PLLMF = 2(CPM_CLK/PCI_CLK) – 1

Refer to Sections 10.1.6 and 10.1.7 for more details.

1 MODCK[1-3] and MODCK_H. Refer to Section 10.1.4, “Dividers.”

2 (CPM_CLK/CLKIN) is defined as the CPM Multiplication Factor in the MPC8280 Family Hardware Specifications.

(CPM_CLK/PCI_CLK) is defined as the CPM Multiplication Factor in the

MPC8280 Family Hardware Specifications.

Table 10-4. 60x Bus-to-Core Frequency

SCMR[CORECNF]

Bus-to-Core Multiplier

0x04, 0x05, 0x15

0x06, 0x11

2.5x

0x08, 0x10

0x0E, 0x1E

3.5x

0x0A, 0x1A

0x07, 0x17

4.5x

0x0B, 0x1B

0x09, 0x19

5.5x

0x0D, 0x1D

0x12

6.5x

0x14

0x16

7.5x

Table 10-3. SCMR Field Descriptions (continued)

Bits

Name

Defaults

Description

PORESET

Hard Reset

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