MPC8280 datasheet(416/1386 Pages) FREESCALE

416 / 1386 page

Clocks and Power Control

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

10-6

Freescale Semiconductor

10.4

System Clock Control Register (SCCR)

The system clock control register (SCCR), shown in Figure 10-5, is memory-mapped into the MPC8280’s

internal space.

Table 10-2 SCCR Field Descriptions describes SCCR fields.

022

Field

—

PCI_MODE PCI_MODCK

PCIDF

CLPD

DFBRG

Reset

Refer to Table 10-2

001

R/W

Addr

0x10C80

Figure 10-5. System Clock Control Register (SCCR)

Table 10-2. SCCR Field Descriptions

Bits

Name

Defaults

Description

POR

Hard Reset

0–22

—

Unaffected

Reserved

PCI_MODE

PCI_Mode

Unaffected

PCI Mode

0 Disabled

1 Enabled

Reflects the inverted value of the PCI_Mode pin.

PCI_MODC

Unaffected

Reflects the value of the PCI_MODCK pin.

25–28

PCIDF

Config pins

Unaffected

PCI division factor.

CLPD

Unaffected

CPM low power disable.

0 Default. CPM does not enter low power mode when the core

enters low power mode.

1 CPM and SIU enter low power mode when the core does. This

may be useful for debug tools that use the assertion of QREQ

as an indication of breakpoint in the core.

30–31

DFBRG

Unaffected

Division factor of BRG_CLK. Determines BRG_CLK frequency.

Changing the value does not result in a loss of lock condition.

BRG_CLK is divided from the PLL output clock (defined as

“MAIN_CLK”), which is 2x the CPM clock. Refer to Figure 10-1.

The decimal equivalent of the binary value of SCCR[30–31]

determines the overall BRG_CLK dividers, as shown in

Figure 10-1. MAIN-CLK is divided by 22(DFBRG + 1).

00 Decimal value of 0; MAIN_CLK divided by 4.

01 Decimal value of 1; MAIN_CLK divided by 16 (normal

operation).

10 Decimal value of 2; MAIN_CLK divided by 64.

11 Decimal value of 3; MAIN_CLK divided by 256.

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