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MPC8280 bảng dữ liệu(PDF) 344 Page - Freescale Semiconductor, Inc |
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MPC8280 bảng dữ liệu(HTML) 344 Page - Freescale Semiconductor, Inc |
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344 / 1386 page ![]() PCI Bridge MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 9-36 Freescale Semiconductor Figure 9-23. Error Status Register (ESR) Table 9-10 describes ESR fields. 31 16 Field — Reset 0000_0000_0000_0000 R/W R/W Addr 0x10886 15 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Field — I2O_ DBMC NMI IRA I2O_ IPQO I2O_ OFQO PERR_ WR PERR_ RD PCI_ SERR TAR_ ABT NO_ RSP DATA_ PAR_ RD DATA_ PAR_ WR ADDR_ PAR Reset 0000_0000_0000_0000 R/W R/W Addr 0x10884 Table 9-10. ESR Field Descriptions Bits Name Description 31–13 — Reserved, should be cleared. 12 I2O_DBMC I2O DoorBell Machine Check. When a PCI-mastered write sets IDBR[31], a machine check is sent to the local processor and the event is reported in ESR[I2O_DBMC]. This bit is also set in the following cases: • An overflow condition in the inbound posted I2O queue • An overflow condition in the outbound free I2O queue. These two interrupts can be masked in the I2O unit. 11 NMI General error/interrupt indication. In host mode, this bit is set when a 60x bus write transaction initiated by the PCI bridge is terminated by the assertion of TEA. In agent mode, this bit is set when the GPCR[MCP2PCI] bit is set and an internal machine check interrupt (MCP) is issued by one of the MPC8280’s MCP sources. Machine check and interrupt assertion is determined by ECR[11]. The reset value of ECR[11], logic zero, indicates that an interrupt will be asserted if ESR[NMI] is set (and enabled per EMR[11]). 10 IRA Illegal register access with incorrect size. 9 I2O_IPQO I2O inbound post queue overflow. 8 I2O_OFQO I2O outbound free queue overflow. 7 PCI_PERR_WR PCI parity error received on a write. 6 PCI_PERR_RD PCI parity error received on a read. 5 PCI_SERR PCI SERR received. 4 PCI_TAR_ABT PCI target abort |
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