MPC8280 datasheet(302/1386 Pages) FREESCALE

302 / 1386 page

The 60x Bus

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

8-26

Freescale Semiconductor

Figure 8-8. Single-Beat and Burst Data Transfers

8.5.4

Effect of ARTRY Assertion on Data Transfer and Arbitration

The MPC8280 allows an address tenure to overlap its associated data tenure. The MPC8280 internally

guarantees that the first TA of the data tenure is delayed to be at the same time or after the ARTRY window

(the clock after the assertion of AACK).

8.5.5

Port Size Data Bus Transfers and PSDVAL Termination

The MPC8280 can transfer data via data ports of 8, 16, 32, and 64 bits, as shown in Section 8.4.3, “Address

Transfer Attribute Signals.” Single-beat transaction sizes can be 8, 16, 32, 64, 128, and 192 bits; burst

transactions are 256 bits. Single-beat and burst transactions are divided into to a number of intermediate

beats depending on the port size. The MPC8280 asserts PSDVAL to mark the cycle in which data is

accepted. Assertion of PSDVAL in conjunction with TA marks the end of the transfer in single-beat mode.

The fourth assertion of PSDVAL in conjunction with TA signals the end of a burst transfer. Figure 8-9

shows an extended transaction of 4 words to a port size of 32 bits. The single-beat transaction is translated

to four port-sized beats.

CLKOUT

ADDR + ATTR

AACK

DBG

D[0–63]

PSDVAL

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