MPC8280 datasheet(298/1386 Pages) FREESCALE

298 / 1386 page

The 60x Bus

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

8-22

Freescale Semiconductor

Figure 8-7. Retry Cycle

As a bus master, the MPC8280 recognizes either an early or qualified ARTRY and prevents the data tenure

associated with the retried address tenure. If the data tenure has begun, the MPC8280 terminates the data

tenure immediately even if the burst data has been received. If the assertion of ARTRY is received up to

or on the bus cycle as the first (or only) assertion of TA for the data tenure, the MPC8280 ignores the first

data beat. If it is a read operation, the MPC8280 does not forward data internally to the cache, execution

unit, or any other MPC8280 internal storage. This address retry case succeeds because the data tenure is

aborted in time, and the entire transaction is rerun. This retry mechanism allows the memory system to

begin operating in parallel with the bus snoopers, provided external devices do not present data sooner than

the bus cycle before all snoop responses can be determined and asserted on the bus.

Note that the system must ensure that ARTRY is never asserted later than the cycle of the first or only

assertion of TA (if the PCI controller can initiate global transactions, the system must ensure that ARTRY

is never asserted on the same cycle or later then the first or only assertion of TA). This guarantees the

relationship between TA and ARTRY such that, in case of an address retry, the data may be cancelled in

the chip before it can be forwarded internally to the internal memory resources (registers or cache).

Generally, the memory system must also detect this event and abort any transfer in progress. If this

CLKOUT

BR INT

ADDR + ATTR

BG INT

ABB

AACK

ARTRY

MPC8280

External

MPC8280

External

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