MPC8280 datasheet(252/1386 Pages) FREESCALE

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External Signals

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

6-10

Freescale Semiconductor

LSDCAS

LGPL3

PCI_MODCK_H3

Local bus SDRAM CAS—Output from the Local bus SDRAM controller. Should be connected to

the CAS inputs of the SDRAMs.

Local bus UPM general purpose line 3—This is one of six general purpose output lines from

UPM. The values and timing of this pin is programmed in the UPM.

PCI MODCK_H3—In PCI mode, defines the operating mode of internal clock circuits.

LGTA

LUPMWAIT

LGPL4

LPBS

Local bus GPCM TA—This input pin is used for transaction termination during GPCM operation.

Requires external pull up resistor for proper operation.

Local bus UPM wait—This is an input to the UPM. An external device may hold this pin high to

force the UPM to wait until the device is ready for the continuation of the operation.

Local bus UPM general purpose line 4—One of six general purpose output lines from UPM. The

values and timing of this pin is programmed in the UPM.

Local bus parity byte select—In systems in which the data parity is stored in a separate chip, this

output is used as the byte select for that chip.

LGPL5

PCI_MODCK

Local bus UPM general purpose line 5—This is one of six general purpose output lines from

UPM. The values and timing of this pin is programmed in the UPM.

PCI MODCK—In PCI mode, defines additional operating modes of internal clock circuits.

LWR

Local write—The local write pin is an output from the local bus memory controller. It is used to

distinguish between read and write transactions.

L_A14

PCI_PAR

Local bus address 14—Local bus address bit 14 output pin. In the local address bus bit 14 is most

significant and bit 31 is least significant.

PCI parity—PCI parity input/output pin. Assertion of this pin indicates that odd parity is driven

across PCI_AD[31-0] and PCI_C/BE[3–0] during address and data phases. Negation of

PCI_PAR indicates that even parity is driven across the PCI_AD[31-0] and PCI_C/BE[3–0] during

address and data phases.

L_A15

SMI

PCI_FRAME

Local bus address 15—Local bus address bit 15 output pin. In the local address bus bit 14 is most

significant and bit 31 is least significant.

System management interrupt—System management interrupt input to the core.

PCI frame—PCI cycle frame input/output pin. Used by the current PCI master to indicate the

beginning and duration of an access. Driven by the MPC8280 when its PCI interface is the master

of the access. Otherwise, it is an input.

L_A16

PCI_TRDY

Local bus address 16—Local bus address bit 16 output pin. In the local address bus bit 14 is most

significant and bit 31 is least significant.

PCI target ready—PCI target ready input/output pin. This pin is driven by the MPC8280 when its

PCI interface is the target of a PCI transfer. Assertion of this pin indicates that the PCI target is

ready to send or accept a data beat.

Table 6-1. External Signals (continued)

Signal

Description

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