XIO2000A datasheet(11/155 Pages) TI

11 / 155 page

Features

April 2007

SCPS155B

XIO2000A Features

D Full x1 PCI Express Throughput

D Fully Compliant with PCI Express to

PCI/PCI-X Bridge Specification,

Revision 1.0

D Fully Compliant with PCI Express Base

Specification, Revision 1.0a

D Fully Compliant with PCI Local Bus

Specification, Revision 2.3

D Extended Virtual Channel (VC) Support

Includes a Second VC for

Quality-of-Service and Isochronous

Applications

D PCI Express Advanced Error Reporting

Capability Including ECRC Support

D Support for D1, D2, D3hot, and D3cold

D Active State Link Power Management

Saves Power When Packet Activity on the

PCI Express Link is Idle, Using Both L0s

and L1 States

D Wake Event and Beacon Support

D Error Forwarding Including PCI Express

Data Poisoning and PCI Bus Parity Errors

D Utilizes 100-MHz Differential PCI Express

Common Reference Clock or 125-MHz

Single-Ended, Reference Clock

D Robust Pipeline Architecture To Minimize

Transaction Latency

D Full PCI Local Bus 66-MHz/32-Bit

Throughput

D Support for Six Subordinate PCI Bus

Masters with Internal Configurable, 2-Level

Prioritization Scheme

D Low Power Design (<350 mW) Ensures

Ease of Implementation

D Two Package Options: 15 mm x 15 mm and

12 mm x 12 mm

D Internal PCI Arbiter Supporting Up to 6

External PCI Masters

D Advanced VC Arbitration Options Include

VC1 Strict Priority, Hardware-Fixed

Round-Robin, and 32-Phase, Weighted

Round-Robin

D Advanced PCI Bus Port Arbitration Options

Include 128-phase, Weighted Round-Robin

Time-Based and 128-phase, Weighted

Round-Robin Aggressive Time-Based

D Advanced PCI Isochronous Windows for

Memory Space Mapping to a Specified

Traffic Class

D Advanced PCI Express Message Signaled

Interrupt Generation for Serial IRQ

Interrupts from CardBus Applications

D External PCI Bus Arbiter Option

D PCI Bus LOCK Support

D Clock Run and Power Override Support

D Six Buffered PCI Clock Outputs (33 MHz or

66 MHz)

D PCI Bus Interface 3.3-V and 5.0-V (33 MHz

only at 5.0 V) Tolerance Options

D Integrated AUX Power Switch Drains VAUX

Power Only When Main Power Is Off

D Eight 3.3-V, Multifunction, General-Purpose

I/O Terminals

D Memory-Mapped EEPROM Serial-Bus

Controller Supporting PCI Express Power

Budget/Limit Extensions for Add-In Cards

D Compact Footprint, 201-Ball, GZZ

MicroStarTM BGA or Lead-Free 201-Ball,

ZZZ MicroStarTM BGA

Table 1−1.

Figure 1−1.

MicroStar BGA is a trademark of Texas Instruments.

Other trademarks are the property of their respective owners.

XIO2000A bảng dữ liệu(PDF) 11 Page - Texas Instruments

XIO2000A bảng dữ liệu(HTML) 11 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL