HT48R53 datasheet(16/35 Pages) HOLTEK

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HT48R52/HT48R53

Rev. 1.20

December 6, 2005

Input/Output Ports

There are 16 bidirectional input/output lines and 24

NMOS input/output in the microcontroller, labeled from

PA to PE, which are mapped to the data memory of

[12H], [14H], [16H], [18H] and [1AH] respectively. All

pins on PA~PE can be used for both input and output

operations.

For the input operation, these ports are non-latching,

that is, the inputs must be ready at the T2 rising edge of

instruction

²MOV A,[m]² (m=12H, 14H, 16H, 18H, 1AH).

For output operation, all the data is latched and remains

unchanged until the output latch is rewritten.

The PA and PB have their own control registers (PAC,

PBC) to control the input/output configuration. These

two control registers are mapped to locations 13H and

15H. CMOS output or Schmitt trigger input with struc-

tures can be reconfigured dynamically under software

control. The control registers specifies which pin are set

as input and which are set as outputs. To setup a pin as

an input the corresponding bit of the control register

must be set high, for an output it must be set low. The

PC, PD and PE can also be used for both input and out-

put operations, these ports are not achieved through the

use of port control registers. Setting up an I/O pin as in-

put is achieved by first setting its output high which ef-

fectively places its NMOS output transistor in high

impedance state allowing the pin to be now used as an

input.

After a chip reset, these input/output lines remain at high

levels or floating state (depending on the pull-high op-

tions). Each bit of these input/output latches can be set

or cleared by

²SET [m].i² and ²CLR [m].i² (m=12H, 14H,

16H, 18H or 1AH) instructions.

Some instructions first input data and then follow the

output operations. For example,

²SET [m].i², ²LR [m].i²,

²CPL [m]², ²CPLA [m]² read the entire port states into

the CPU, execute the defined operations (bit-operation),

and then write the results back to the latches or the ac-

cumulator.

Each line of port A has the capability of waking-up the

device.

There is a pull-high option available for all I/O lines (port

option). Once the pull-high option of an I/O line is se-

lected, the I/O line have pull-high resistor. Otherwise,

V D D

P C 0 ~ P C 7

P D 0 ~ P D 7

P E 0 ~ P E 7

C K

D a t a B i t

P U

D a t a B u s

W r i t e D a t a R e g i s t e r

C h i p S e l e c t

R e a d D a t a R e g i s t e r

P u l l - u p

PC, PD, PE Input/Output Ports

V D D

P A 0 ~ P A 7

P B 0 ~ P B 7

B u z z e r O p t i o n

( P B 0 , P B 1 O n l y )

W a k e - u p O p t i o n

S y s t e m W a k e - u p

( P A o n l y )

R e a d D a t a R e g i s t e r

P B 0 / P B 1

B Z / B Z

( P B 0 , P B 1 O n l y )

C K

C o n t r o l B i t

P U

D a t a B u s

W r i t e C o n t r o l R e g i s t e r

C h i p R e s e t

R e a d C o n t r o l R e g i s t e r

W r i t e D a t a R e g i s t e r

D a t a B i t

PA, PB Input/Output Ports

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