PPC440GX-3RF800C datasheet(73/93 Pages) AMCC

73 / 93 page

440GX – Power PC 440GX Embedded Processor

AMCC

Revision 1.15 – August 30, 2007

Data Sheet

Ethernet RGMII Interface

GMC0RxClk

async

GMC0RxCtl

GMC0RxClk

4, 5

GMC0RxD0:3

5.1

6.8

GMC0RxClk

4, 5

GMC0TxClk

5.1

6.8

async

GMC0TxCtl

0.5

3.5

5.1

6.8

GMC0TxClk

4, 5

GMC0TxD0:3

0.5

3.5

5.1

6.8

GMC0TxClk

4, 5

GMC1RxClk

async

GMC1RxCtl

GMC1RxClk

4, 5

GMC1RxD0:3

5.1

6.8

GMC1RxClk

4, 5

GMC1TxClk

5.1

6.8

async

GMC1TxCtl

0.5

3.5

5.1

6.8

GMC1TxClk

4, 5

GMC1TxD0:3

0.5

3.5

5.1

6.8

GMC1TxClk

4, 5

GMCRefClk

async

Ethernet TBI Interface

TBIRxClk0

async

TBIRxClk1

async

TBIRxD0:9

2.5

1.5

5.1

6.8

TBIRxClkx

TBITxClk

async

TBITxD0:9

5.1

6.8

TBITxClk

I/O Specifications—All Speeds (Sheet 4 of 7)

Notes:

1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard.

2. PCI-X timings are for asynchronous operation up to 133MHz. PCI-X input setup time requirement is 1.2ns for 133MHz and

1.7ns for 66MHz. PCI timings (in parentheses) are for asynchronous operation up to 66MHz. PCI output hold time

requirement is 1ns for 66MHz and 2ns for 33MHz.

3. The clock frequency for RMII operation is 50MHz ± 100ppm.

4. The clock frequency for SMII operation is 125MHz ± 100ppm.

5. These are DDR signals that can change on both the positive and negative clock transitions.

Signal

Input (ns)

Output (ns)

Output Current (mA)

Clock

Notes

Setup Time

(TIS min)

Hold Time

(TIH min)

Valid Delay

(TOV max)

Hold Time

(TOH min)

I/O H

(minimum)

I/O L

(minimum)

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