PPC440GX-3RF800C datasheet(71/93 Pages) AMCC

71 / 93 page

440GX – Power PC 440GX Embedded Processor

AMCC

Revision 1.15 – August 30, 2007

Data Sheet

Ethernet MII Interface

EMCRxD0:3

5.1

6.8

EMCRxClk

EMCRxDV

5.1

6.8

EMCRxClk

5.1

6.8

async

EMCRxErr

5.1

6.8

EMCRxClk

EMCTxD0:3

5.1

6.8

EMCTxClk

EMCTxEn

5.1

6.8

EMCTxClk

async

EMCTxErr

5.1

6.8

EMCTxClk

EMCCrS

5.1

6.8

async

EMCCD

5.1

6.8

async

EMCMDIO

5.1

6.8

EMCMDClk

5.1

6.8

async

Ethernet RMII Interface

EMC0RxD0:1

5.1

6.8

EMCRefClk

EMC0RxErr

5.1

6.8

EMCRefClk

EMC0CrSDV

5.1

6.8

EMCRefClk

EMC0TxD0:1

5.1

6.8

EMCRefClk

EMC0:1TxEn

5.1

6.8

EMCRefClk

EMC1RxD0:1

5.1

6.8

EMCRefClk

EMC1RxErr

5.1

6.8

EMCRefClk

EMC1CrSDV

5.1

6.8

EMCRefClk

EMC1TxD0:1

5.1

6.8

EMCRefClk

async

I/O Specifications—All Speeds (Sheet 2 of 7)

Notes:

1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard.

2. PCI-X timings are for asynchronous operation up to 133MHz. PCI-X input setup time requirement is 1.2ns for 133MHz and

1.7ns for 66MHz. PCI timings (in parentheses) are for asynchronous operation up to 66MHz. PCI output hold time

requirement is 1ns for 66MHz and 2ns for 33MHz.

3. The clock frequency for RMII operation is 50MHz ± 100ppm.

4. The clock frequency for SMII operation is 125MHz ± 100ppm.

5. These are DDR signals that can change on both the positive and negative clock transitions.

Signal

Input (ns)

Output (ns)

Output Current (mA)

Clock

Notes

Setup Time

(TIS min)

Hold Time

(TIH min)

Valid Delay

(TOV max)

Hold Time

(TOH min)

I/O H

(minimum)

I/O L

(minimum)

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