PPC440GP-3CC466C datasheet(66/83 Pages) AMCC

66 / 83 page

440GP – Power PC 440GP Embedded Processor

AMCC

Revision 1.07 – October 4, 2007

Data Sheet

Ethernet MII Interface

EMCRxD0:3

n/a

EMCRxClk

EMCRxDV

n/a

EMCRxClk

n/a

async

EMCRxErr

n/a

EMCRxClk

EMCTxD0:3

10.3

7.1

EMCTxClk

EMCTxEn

10.3

7.1

EMCTxClk

async

EMCTxErr

10.3

7.1

EMCTxClk

EMCCrS

n/a

async

EMCCD

n/a

async

EMCMDIO

10.3

7.1

EMCMDClk

10.3

7.1

async

Ethernet RMII Interface

EMC0RxD0:1

n/a

EMCRxClk

EMC0RxErr

n/a

EMCRxClk

EMC0CrSDV

n/a

EMCRxClk

EMC0TxD0:1

10.3

7.1

EMCTxClk

EMC0:1TxEn

10.3

7.1

EMCTxClk

EMC1RxD0:1

10.3

7.1

EMCRxClk

EMC1RxErr

n/a

EMCRxClk

EMC1CrSDV

n/a

EMCRxClk

EMC1TxD0:1

10.3

7.1

EMCTxClk

EMCRefClk

10.3

7.1

async

I/O Specifications—All Speeds (Sheet 2 of 4)

Notes:

1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard.

2. PCI-X timings are for asynchronous operation up to 133MHz. PCI-X input setup time requirement is 1.2ns for 133MHz and

1.7ns for 66MHz. PCI timings (in parentheses) are for asynchronous operation up to 66MHz. PCI output hold time

requirement is 1ns for 66MHz and 2ns for 33MHz.

3. The clock frequency for RMII operation is 50MHz ± 100ppm.

Signal

Input (ns)

Output (ns)

Output Current (mA)

Clock

Notes

Setup Time

(TIS min)

Hold Time

(TIH min)

Valid Delay

(TOV max)

Hold Time

(TOH min)

I/O H

(minimum)

I/O L

(minimum)

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