PPC440GP-3CC466C datasheet(54/83 Pages) AMCC

54 / 83 page

440GP – Power PC 440GP Embedded Processor

AMCC

Revision 1.07 – October 4, 2007

Data Sheet

Trace Interface

TrcBS0:2

Trace branch execution status.

I/O

5V tolerant

3.3V LVTTL

TrcClk

Trace data capture clock, runs at 1/4 the frequency of the

processor.

5V tolerant

3.3V LVTTL

TrcES0:4

Trace Execution Status is presented every fourth processor clock

cycle.

I/O

5V tolerant

3.3V LVTTL

TrcTS0:6

Additional information on trace execution and branch status.

I/O

5V tolerant

3.3V LVTTL

Power Pins

AGND

PLL (analog) voltage ground.

GND

Ground.

AxVDD

1.8V—Filtered voltages input for PLLs (analog circuits)

Note: A separate filter for each of the three voltages is

recommended.

OVDD

3.3V supply—I/O (except DDR SDRAM)

SVDD

2.5V supply—DDR SDRAM

VDD

1.8V supply—Logic voltage.

Reserved Pins

Reserved

Do not connect signals, voltage, or ground to these balls.

Signal Functional Description (Sheet 7 of 7)

Notes:

1. Receiver input has hysteresis

2. Must pull up (recommended value is 3k

Ω to 3.3V, 10kΩ to 5V)

3. Must pull down (recommended value is 1k

Ω)

4. If not used, must pull up (recommended value is 3k

Ω to 3.3V)

5. If not used, must pull down (recommended value is 1k

Ω)

6. Strapping input during reset; pull-up or pull-down required

Signal Name

Description

I/O

Type

Notes

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