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ST72324BK bảng dữ liệu(PDF) 14 Page - STMicroelectronics |
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ST72324BK bảng dữ liệu(HTML) 14 Page - STMicroelectronics |
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14 / 188 page ![]() Pin description ST72324B 14/188 41 34 23 26 OSC2(3) O Resonator oscillator inverter output 42 35 24 27 OSC1(3) I External clock input or Resonator oscillator inverter input 43 36 25 28 VDD_2 (1) S Digital Main Supply Voltage 44 37 26 29 PE0/TDO I/O CT X X X X Port E0 SCI Transmit Data Out 1 38 27 30 PE1/RDI I/O CT X X X X Port E1 SCI Receive Data In 2 39 28 31 PB0 I/O CT Xei2 X X Port B0 Caution: Negative current injection not allowed on this pin(4) 3 40 PB1 I/O CT Xei2 X X Port B1 4 41 PB2 I/O CT Xei2 X X Port B2 5 42 29 32 PB3 I/O CT X ei 2 XX Port B3 1. It is mandatory to connect all available VDD and VREF pins to the supply voltage and all VSS and VSSA pins to ground. 2. On the chip, each I/O port has eight pads. Pads that are not bonded to external pins are in input pull-up configuration after reset. The configuration of these pads must be kept at reset state to avoid added current consumption. 3. OSC1 and OSC2 pins connect a crystal/ceramic resonator, or an external source to the on-chip oscillator; see Section 1: Description and Section 12.6: Clock and timing characteristics for more details. 4. For details refer to Section 12.9.1 on page 153 Table 1. Device pin description (continued) Pin No. Pin Name Level Port Main function (after reset) Alternate Function Input Output |
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