ST72324BK datasheet(93/188 Pages) STMICROELECTRONICS

93 / 188 page

ST72324B

On-chip peripherals

93/188

The communication is always initiated by the master. When the master device transmits

data to a slave device via MOSI pin, the slave device responds by sending data to the

master device via the MISO pin. This implies full duplex communication with both data out

and data in synchronized with the same clock signal (which is provided by the master device

via the SCK pin).

To use a single data line, the MISO and MOSI pins must be connected at each node (in this

case only simplex communication is possible).

Four possible data/clock timing relationships may be chosen (see Figure 54) but master and

slave must be programmed with the same timing mode.

Figure 51.

Single master/single slave application

Slave Select management

As an alternative to using the SS pin to control the Slave Select signal, the application can

choose to manage the Slave Select signal by software. This is configured by the SSM bit in

the SPICSR register (see Figure 53).

In software management, the external SS pin is free for other application uses and the

internal SS signal level is driven by writing to the SSI bit in the SPICSR register.

In Master mode:

–SS internal must be held high continuously

Depending on the data/clock timing relationship, there are two cases in Slave mode (see

Figure 52):

If CPHA = 1 (data latched on second clock edge):

–SS internal must be held low during the entire transmission. This implies that in

single slave applications the SS pin either can be tied to VSS, or made free for

standard I/O by managing the SS function by software (SSM = 1 and SSI = 0 in

the in the SPICSR register)

If CPHA = 0 (data latched on first clock edge):

–SS internal must be held low during byte transmission and pulled high between

each byte to allow the slave to write to the shift register. If SS is not pulled high, a

Write Collision error will occur when the slave writes to the shift register (see Write

collision error (WCOL) on page 97).

8-bit Shift Register

SPI

clock

generator

8-bit Shift Register

MISO

MOSI

MISO

SCK

Slave

Master

+5V

MSB

LSB

MSB

LSB

Not used if SS is managed

by software

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