ST72324BK datasheet(54/188 Pages) STMICROELECTRONICS

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I/O ports

ST72324B

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External interrupt function

When an I/O is configured as ‘Input with Interrupt’, an event on this I/O can generate an

external interrupt request to the CPU.

Each pin can independently generate an interrupt request. The interrupt sensitivity is

independently programmable using the sensitivity bits in the EICR register.

Each external interrupt vector is linked to a dedicated group of I/O port pins (see pinout

description and interrupt section). If several input pins are selected simultaneously as

interrupt sources, these are first detected according to the sensitivity bits in the EICR

The external interrupts are hardware interrupts, which means that the request latch (not

accessible directly by the application) is automatically cleared when the corresponding

interrupt vector is fetched. To clear an unwanted pending interrupt by software, the

sensitivity bits in the EICR register must be modified.

9.2.2

Output modes

The output configuration is selected by setting the corresponding DDR register bit. In this

case, writing the DR register applies this digital value to the I/O pin through the latch. Then

reading the DR register returns the previously stored value.

Two different output modes can be selected by software through the OR register: Output

push-pull and open-drain.

9.2.3

Alternate functions

When an on-chip peripheral is configured to use a pin, the alternate function is automatically

selected. This alternate function takes priority over the standard I/O programming.

When the signal is coming from an on-chip peripheral, the I/O pin is automatically

configured in output mode (push-pull or open drain according to the peripheral).

When the signal is going to an on-chip peripheral, the I/O pin must be configured in input

mode. In this case, the pin state is also digitally readable by addressing the DR register.

Note:

Input pull-up configuration can cause unexpected value at the input of the alternate

peripheral input. When an on-chip peripheral use a pin as input and output, this pin has to

be configured in input floating mode.

Table 26.

DR register value and output pin status

Push-pull

Open-drain

0VSS

VSS

1VDD

Floating

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