ST72324BK datasheet(115/188 Pages) STMICROELECTRONICS

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ST72324B

On-chip peripherals

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10.5.5

Low power modes

10.5.6

Interrupts

The SCI interrupt events are connected to the same interrupt vector.

These events generate an interrupt if the corresponding Enable Control bit is set and the

interrupt mask in the CC register is reset (RIM instruction).

10.5.7

SCI registers

SCI Status Register (SCISR)

Table 59.

Effect of low power modes on SCI

Mode

Description

Wait

No effect on SCI.

SCI interrupts cause the device to exit from Wait mode.

Halt

SCI registers are frozen.

In Halt mode, the SCI stops transmitting/receiving until Halt mode is exited.

Table 60.

SCI interrupt control/wake-up capability

Interrupt event

Event flag Enable control bit Exit from WAIT Exit from HALT

Transmit data register empty

TDRE

TIE

Yes

Transmission complete

TCIE

Yes

Received data ready to be read

RDRF

RIE

Yes

Overrun error detected

Yes

Idle line detected

IDLE

ILIE

Yes

Parity error

PIE

Yes

SCISR

Reset value: 1100 0000 (C0h)

654

TDRE

RDRF

IDLE

Table 61.

SCISR register description

Bit

Name

Function

TDRE

Transmit Data Register Empty

This bit is set by hardware when the content of the TDR register has been transferred

into the shift register. An interrupt is generated if the TIE bit = 1 in the SCICR2

followed by a write to the SCIDR register).

0: Data is not transferred to the shift register.

1: Data is transferred to the shift register.

Note: Data will not be transferred to the shift register unless the TDRE bit is cleared.

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