LIS331DL datasheet(32/38 Pages) STMICROELECTRONICS

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LIS331DL

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7.15

FF_WU_SRC_2 (35h)

Free-fall and wake-up source register. Read only register.

Reading at this address clears FF_WU_SRC_2 register and the FF_WU_2 interrupt and

allows the refreshment of data in the FF_WU_SRC_2 register if the latched option was

chosen.

7.16

FF_WU_THS_2 (36h)

Most significant bit (DCRM) is used to select the resetting mode of the duration counter. If

DCRM=0 counter is reset when the interrupt is no more active else if DCRM=1 duration

counter is decremented.

Table 34.

FF_WU_SRC_2 register

Table 35.

FF_WU_SRC_2 descrption

Interrupt Active. Default value: 0

(0: no interrupt has been generated;

1: one or more interrupt events have been generated)

Z High. Default value: 0

(0: no interrupt; 1: ZH event has occurred)

Z Low. Default value: 0

(0: no interrupt; 1: ZL event has occurred)

Y High. Default value: 0

(0: no interrupt; 1: YH event has occurred)

Y Low. Default value: 0

(0: no interrupt; 1: YL event has occurred)

X High. Default value: 0

(0: no interrupt; 1: XH event has occurred)

X Low. Default value: 0

(0: no interrupt; 1: XL event has occurred)

Table 36.

FF_WU_THS_2 register

DCRM

THS6

THS5

THS4

THS3

THS2

THS1

THS0

Table 37.

FF_WU_THS_2 description

DCRM

Resetting mode selection. Default value: 0

(0: counter reset; 1: counter decremented)

THS6, THS0

Free-fall / wake-up Threshold. Default value: 000 0000

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