LIS331DL datasheet(30/38 Pages) STMICROELECTRONICS

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LIS331DL

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7.11

FF_WU_SRC_1 (31h)

Free-fall and wake-up source register. Read only register.

Reading at this address clears FF_WU_SRC_1 register and the FF, WU 1 interrupt and

allows the refreshment of data in the FF_WU_SRC_1 register if the latched option was

chosen.

7.12

FF_WU_THS_1 (32h)

Most significant bit (DCRM) is used to select the resetting mode of the duration counter. If

DCRM=0 counter is reset when the interrupt is no more active else if DCRM=1 duration

counter is decremented.

Table 26.

FF_WU_SRC_1 register

Table 27.

FF_WU_SRC_1 description

Interrupt Active. Default value: 0

(0: no interrupt has been generated; 1: one or more interrupts have been generated)

Z High. Default value: 0

(0: no interrupt, 1: ZH event has occurred)

Z Low. Default value: 0

(0: no interrupt; 1: ZL event has occurred)

Y High. Default value: 0

(0: no interrupt, 1: YH event has occurred)

Y Low. Default value: 0

(0: no interrupt, 1: YL event has occurred)

X High. Default value: 0

(0: no interrupt, 1: XH event has occurred)

X Low. Default value: 0

(0: no interrupt, 1: XL event has occurred)

Table 28.

FF_WU_THS_1 register

DCRM

THS6

THS5

THS4

THS3

THS2

THS1

THS0

Table 29.

FF_WU_THS_1 description

DCRM

Resetting mode selection. Default value: 0

(0: counter reset; 1: counter decremented)

THS6, THS0

Free-fall / wake-up Threshold: default value: 000 0000

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