P89V52X2FN datasheet(32/56 Pages) PHILIPS

32 / 56 page

P89V52X2_1

Preliminary data sheet

Rev. 01 — 7 June 2007

32 of 56

NXP Semiconductors

P89V52X2

80C51 with 256 B RAM, 192 B data EEPROM

6.12 Power-saving modes

The device provides two power saving modes of operation for applications where power

consumption is critical. The two modes are idle and Power-down, see Table 31.

6.12.1 Idle mode

Idle mode is entered setting the IDL bit in the PCON register. In Idle mode, the program

counter is stopped. The system clock continues to run and all interrupts and peripherals

remain active. The on-chip RAM and the special function registers hold their data during

this mode.

EX1

External Interrupt 1 Enable.

ET0

Timer 0 Overflow Interrupt Enable.

EX0

External Interrupt 0 Enable.

Table 27.

IP - Interrupt priority low register (address B8H) bit allocation

Bit addressable; Reset value: 00H

Bit

Symbol

PT2

PT1

PX1

PT0

PX0

Table 28.

IP - Interrupt priority low register (address B8H) bit description

Bit

Symbol

Description

7:6

Reserved

PT2

Timer 2 Interrupt Priority Low Bit

Serial Port Interrupt Priority Low Bit.

PT1

Timer 1 Interrupt Priority Low Bit.

PX1

External Interrupt 1 Priority Low Bit.

PT0

Timer 0 Interrupt Priority Low Bit.

PX0

External Interrupt 0 Priority Low Bit.

Table 29.

IPH - Interrupt priority high register (address B7H) bit allocation

Not bit addressable; Reset value: 00H

Bit

Symbol

PT2H

PSH

PT1H

PX1H

PT0H

PX0H

Table 30.

IPH - Interrupt priority high register (address B7H) bit description

Bit

Symbol

Description

7:6

Reserved

PT2H

Timer 2 Interrupt Priority High Bit.

PSH

Serial Port Interrupt Priority High Bit.

PT1H

Timer 1 Interrupt Priority High Bit.

PX1H

External Interrupt 1 Priority High Bit.

PT0H

Timer 0 Interrupt Priority High Bit.

PX0H

External Interrupt 0 Priority High Bit.

Table 26.

IE - Interrupt enable register (address A8H) bit description …continued

Bit

Symbol

Description

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