P89V52X2FN datasheet(41/56 Pages) PHILIPS

41 / 56 page

P89V52X2_1

Preliminary data sheet

Rev. 01 — 7 June 2007

41 of 56

NXP Semiconductors

P89V52X2

80C51 with 256 B RAM, 192 B data EEPROM

6.16 Code security (CSEC) bits

The code security bits protects against software piracy and prevents the contents of the

flash from being read by unauthorized parties. The code security bits and their effects are

shown in Table 41.

Table 40.

UCFG - User configuration register bit description

Bit

Symbol

Description

7 to 3

Reserved

ENW

Enable Write. When programmed = 1, forces the WE bit to be set.

FX2

Force X2. When programmed = 1, the device is in 6-clock mode.

When erased = 0, the mode depends on the state of the X2 bit in

CKCON.

EXTCLK

External Clock. When programmed = 1, disables the XTAL block when

using an external digital clock source.

Table 41.

CSEC - Code security register bit allocation

Bit

Symbol

----

INTEXEC

PROT

Table 42.

CSEC - Code security register bit description

Bit

Symbol

Description

7 to 2

Reserved

INTEXEC

Internal execution only. When programmed, if the internal address

space is exceeded, the address will rollover into internal space (upper

address bits are ignored) for MOVC and instruction fetches. MOVC

will access the data EEPROM when the address >= FF00H.

PROT

Protect. When programmed, prohibits further erasing or programming

of code memory.

MOVC instructions executed from external

code memory are disabled from fetching code bytes from

internal code memory.

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