P89V52X2FN datasheet(18/56 Pages) PHILIPS

18 / 56 page

P89V52X2_1

Preliminary data sheet

Rev. 01 — 7 June 2007

18 of 56

NXP Semiconductors

P89V52X2

80C51 with 256 B RAM, 192 B data EEPROM

6.8.3 Mode 2

Mode 2 configures the Timer register as an 8-bit Counter (TLn) with automatic reload, as

shown in Figure 12. Overflow from TLn not only sets TFn, but also reloads TLn with the

contents of THn, which must be preset by software. The reload leaves THn unchanged.

Mode 2 operation is the same for Timer 0 and Timer 1.

6.8.4 Mode 3

When timer 1 is in Mode 3 it is stopped (holds its count). The effect is the same as setting

TR1 = 0.

Timer 0 in Mode 3 establishes TL0 and TH0 as two separate 8-bit counters. The logic for

Mode 3 and Timer 0 is shown in Figure 13. TL0 uses the Timer 0 control bits: T0C/T,

T0GATE, TR0, INT0, and TF0. TH0 is locked into a timer function (counting machine

cycles) and takes over the use of TR1 and TF1 from Timer 1. Thus, TH0 now controls the

‘Timer 1’ interrupt.

Mode 3 is provided for applications that require an extra 8-bit timer. With Timer 0 in

Mode 3, the P89V52X2 can look like it has an additional Timer.

Note: When Timer 0 is in Mode 3, Timer 1 can be turned on and off by switching it into

and out of its own Mode 3. It can still be used by the serial port as a baud rate generator,

or in any application not requiring an interrupt.

Fig 11. Timer/Counter 0 or 1 in Mode 1 (16-bit counter)

002aaa520

osc/6

Tn pin

TRn

TnGate

INTn pin

C/T = 0

C/T = 1

TLn

(8-bits)

THn

(8-bits)

TFn

control

overflow

interrupt

Fig 12. Timer/Counter 0 or 1 in Mode 2 (8-bit auto-reload)

002aaa521

osc/6

Tn pin

TRn

TnGate

INTn pin

TLn

(8-bits)

THn

(8-bits)

TFn

control

overflow

reload

interrupt

C/T = 0

C/T = 1

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