3.0 Software Interface
RC96V24DP
3.5 Interface Memory Access to DSP RAM
Single Device Data/Modem Data Pump
3-8
D96V24DSA
3.5 Interface Memory Access to DSP RAM
The DSP Interface memory acts as an intermediary during host to DSP RAM or
DSP RAM to host data exchanges. The addresses stored in modem Interface
memory RAM Address registers (i. e., XADD and YADD) by the host, in
conjunction with the data or coefficient RAM bits (i. e., XCR and YCR)
determine the DSP RAM addresses for data access.
3.6 Host Programmable Data
The parameters available In DSP RAM are listed in Table 3-3 along with the X
RAM or Y RAM address and corresponding XCR or YCR bit value. The scaling
for the host programmable data is described in the Modem Designer’s Guide.
Table 3-3. DSP RAM Parameters
No.
XCR/YCR(1)
X RAM
Addr
Y RAM
Addr
Parameter
1
1
0-1E
Adaptive Equalizer Coefficients, Real
1
0
–
First coefficient, Real (1) (Data/Fax)
1
10
–
Last Coefficient, Real (17) (Data)
1
1E
–
Last Coefficient, Real (31) (Fax)
2
1
0-1E
Adaptive Equalizer Coefficients, Imag.
1
–
0
First Coefficient, Imag. (1) (Data/Fax)
1
–
10
Last Coefficient, Imag. (17) (Data)
1
–
1E
Last Coefficient, Imag. (31) (Fax)
3
0
49
–
Rotated Error, Real
4
0
–
49
Rotated Error, Imaginary
50
3F
–
Max AGC Gain Word
6
0
71
–
Pulse Dial Interdigit Time
7
0
7C
–
Tone Dial Interdigit Time
8
0
72
–
Pulse Dial Relay Make Time
9
0
7D
–
Pulse Dial Relay Break Time
10
0
7E
–
DTMF Duration
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