PM8621 datasheet(42/184 Pages) PMC

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NSE-8G™ Standard Product Data Sheet

Preliminary

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use

Document ID: PMC-2010850, Issue 1

At the system level, reliable operation will be obtained if proper signal integrity is maintained

through the signal path and the receiver requirements are respected. Namely, a worst case eye

opening of 0.7UI and 100 mV differential amplitude is needed. These conditions should be

achievable with a system architecture consisting of board traces, two sets of backplane

connectors, up to 1m of backplane interconnect. This assumes proper design of 100

Ω differential

lines and minimization of discontinuities in the signal path. Due to power constraints, the output

differential amplitude is approximately 350 mV

The LVDS system is comprised of the LVDS Receiver (RXLV), LVDS Transmitter (TXLV),

Transmitter reference (TXREF), data recovery unit (DRU), parallel to serial converter (PISO and

Clock Synthesis Unit (CSU).

9.1.1

LVDS Receiver (RXLV)

The RXLV block is a 777.6 Mbit/s Low Voltage Differential Signaling (LVDS) Receiver

according to the IEEE 1596.3-1996 LVDS Specification.

The RXLV block is the receiver in Figure 7, accepting 777.6 Mbit/s LVDS signals from the

transmitter, over RP[X]/RN[X] pins, amplifying them and converting them to digital signals, then

passing them to a data recovery unit (DRU). Holding to the IEEE 1596.3-1996 specification, the

RXLV has a differential input sensitivity better than 100 mV, and includes at least 25 mV of

hysteresis. There are 12 RXLV blocks in the NSE.

9.1.2

LVDS Transmitter (TXLV)

The TXLV block is a 777.6 Mbit/s Low Voltage Differential Signaling (LVDS) Transmitter

according to the IEEE 1596.3-1996 LVDS Specification.

The TXLV accepts 777.6 Mbit/s differential data from a “parallel-in, serial-out” (PISO) circuit

and then transmits the data off-chip as a LVDS on TP[X]/TN[X] pins.

The TXLV uses a reference current and voltage from the TXREF block to control the output

differential voltage amplitude and the output common-mode voltage.

There are 12 instances of the TXLV block in the NSE-8G.

9.1.3

LVDS Transmit Reference (TXREF)

The TXREF provides an on-chip bandgap voltage reference (1.20 V ±5%) and a precision current

to the TXLV (777.6 Mbit/s LVDS Transmitter) block’s. The reference Voltage is used to control

the common-mode level of the TXLV output, while the reference current is used to control the

output amplitude.

The precision currents are generated by forcing the reference Voltage across an external, off-chip

3.16 k

Ω(±1%) resistor. The resulting current is then mirrored through several individual reference

current outputs, so each TXLV receives its own reference current.

There is one instance of the TXREF in the NSE-8G.

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