PM8621 datasheet(39/184 Pages) PMC

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NSE-8G™ Standard Product Data Sheet

Preliminary

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use

Document ID: PMC-2010850, Issue 1

Pad Name

Type

Pin No.

Function

NC[49:0]

D17

B17

A17

D25

C25

D26

B26

A26

C27

B27

C28

B28

A28

TOTAL

480

Notes

All NSE-8G inputs and bi-directional balls except the LVDS links present minimum capacitive loading

and operate at TTL logic levels.

Inputs RSTB, ALE, TMS, TDI and TRSTB have internal pull-up resistors.

All outputs have a minimum 8 mA drive capability – this includes TDO, INTB and D[31:0]).

The VDDI and AVDL power pins are not internally connected to each other. Failure to connect these

pins externally may cause malfunction or damage to the device.

The AVDH, CSU_AVDH and VDDO power pins are not internally connected to each other. Failure to

connect these pins externally may cause malfunction or damage to the device.

The VDDI, VDDO, AVDH, CSU_AVDH and AVDL power pins all share the common ground VSS.

To prevent damage to the device and to ensure proper operation, power must be applied

simultaneously to all 3.3 V power pins followed by power to all the 1.8 V power pins followed by input

pins driven by signals.

To prevent damage to the device, power must first be removed from input pins followed by the removal

of power from all the 1.8 V power supply pins followed by the simultaneous removal of power from all

the 3.3 V power pins.

The 3.3 V supplies should never be less than the 1.8 V supplies at any time during power-up and

power-down.

8.2

Analog Power Filtering Recommendations

To achieve best performance of the LVDS links, an analog filter network should be installed

between the power balls and the supply.

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