ADC3910CSSS datasheet(36/47 Pages) TI

36 / 47 page

DC/DC

Regulator

5V-12V

LDO

GND

AVDD

IOVDD

47uF

10uF 10uF

0.1uF

10uF 10uF

0.1uF

2.1V

1.8V

FB = Ferrite bead filter

GND

Figure 8-5. Example: LDO Linear Regulator Approach

DC/DC

Regulator

5V-12V

GND

AVDD

IOVDD

EMI FILTER

10uF 10uF

0.1uF

10uF 10uF

0.1uF

1.8V

GND

10uF 10uF 10uF

Ripple filter notch frequency to match switching frequency of the DC/DC regulator

FB = Ferrite bead filter

Figure 8-6. Example: Switcher-Only Approach

8.4 Layout

8.4.1 Layout Guidelines

There are several critical signals which require specific care during board design:

1. Analog input and clock signals

• Traces should be as short as possible and vias should be avoided where possible to minimize impedance

discontinuities.

2. Digital output interface

• Traces should be as short as possible to reduce capacitive load seen by the CMOS outputs.

• Series resistance should be used to reduce instantaneous current demand and improve signal integrity.

3. Power and ground connections

• Provide low resistance connection paths to all power and ground pins.

• Use power and ground planes instead of traces.

• Avoid narrow, isolated paths which increase the connection resistance.

• Use a signal/ground/power circuit board stackup to maximize coupling between the ground and power

plane.

8.4.2 Layout Example

The following screen shot shows the top layer of the ADC3910D125EVM.

• Signal inputs are routed as different signal and along with clock input on the top layer avoiding vias.

• Serial CMOS output interface lanes with isolation resistor.

• Bypass caps are close to the VREF pin on the top layer avoiding vias.

ADC3908D025, ADC3908D065, ADC3908D125

ADC3908S025, ADC3908S065, ADC3908S125

SBASAU9 – OCTOBER 2024

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Product Folder Links: ADC3908D025 ADC3908D065 ADC3908D125 ADC3908S025 ADC3908S065 ADC3908S125

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