PM5352 datasheet(49/77 Pages) PMC

49 / 77 page

PM5352 S/UNI STAR

DATA SHEET

PMC-1990421

ISSUE 2

SATURN USER NETWORK INTERFACE 155 (STAR)

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

MICROPROCESSOR INTERFACE

The microprocessor interface block provides normal and test mode

registers, and the logic required to connect to the microprocessor

interface. The normal mode registers are required for normal operation,

and test mode registers are used to enhance the testability of the

S/UNI-STAR. The register set is accessed as shown in Table 1. In the

following section every register is documented and identified using the

must be treated as Reserved.

Table 1: Register Memory Map

REG

Address

A[10:0]

Description

000

S/UNI-STAR Master Reset and Identity

001

S/UNI-STAR Master Configuration

002

S/UNI-STAR Master System Interface Config

003

S/UNI-STAR Master Clock Monitor

004

S/UNI-STAR Master Interrupt Status

305

S/UNI-STAR Channel Reset and Performance

Monitoring Update

206

S/UNI-STAR Channel Configuration

307

S/UNI-STAR Channel Control

308

S/UNI-STAR Channel Control Extensions

309

Reserved

30A

S/UNI-STAR Channel Interrupt Status 1

30B

S/UNI-STAR Channel Interrupt Status 2

00C

CSPI Control and Status (Clock Synthesis)

00D

Reserved

30E

CRSI Control and Status (Clock Recovery)

30F

Reserved

310

RSOP Control/Interrupt Enable

311

RSOP Status/Interrupt Status

312

RSOP Section BIP-8 LSB

313

RSOP Section BIP-8 MSB

314

TSOP Control

315

TSOP Diagnostic

316

Reserved

317

Reserved

318

RLOP Control/Status

319

RLOP Interrupt Enable/Status

31A

RLOP Line BIP-24 LSB

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