CS42448 datasheet(47/64 Pages) CIRRUS

47 / 64 page

DS648F2

CS42448

6.6.6

ADC3 Single-Ended Mode (ADC3 SINGLE)

Default = 0

0 - Disabled; Differential input to ADC

1 - Enabled; Single-Ended input to ADC

Function:

When disabled, this bit removes the 4:2 multiplexer from the signal path of ADC3 allowing a differential

input. When enabled, this bit allows the user to choose between four single-ended inputs to ADC3, using

the AIN5_MUX and AIN6_MUX bits. See Figure 12 on page 27 and Figure 27 on page 53 for graphical

descriptions.

6.6.7

Analog Input Ch. 5 Multiplexer (AIN5_MUX)

Default = 0

0 - Single-Ended Input AIN5A

1 - Single-Ended Input AIN5B

Function:

ADC3 can accept single-ended input signals when the ADC3 SINGLE bit is enabled. The AIN5_MUX bit

selects between two input channels (AIN5A or AIN5B) to be sent to ADC3 in Single-Ended Mode. This bit

is ignored when the ADC3_SINGLE bit is disabled. See Figure 12 on page 27 for a graphical description.

6.6.8

Analog Input Ch. 6 Multiplexer (AIN6_MUX)

Default = 0

0 - Single-Ended Input AIN6A

1 - Single-Ended Input AIN6B

Function:

ADC3 can accept a single-ended input signal when the ADC3 SINGLE bit is enabled. The AIN6_MUX bit

selects between two input channels (AIN6A or AIN6B) to be sent to ADC3 in Single-Ended Mode. This bit

is ignored when the ADC3_SINGLE bit is disabled. See Figure 12 on page 27 for a graphical description.

6.7

Transition Control (Address 06h)

6.7.1

Single Volume Control (DAC_SNGVOL, ADC_SNGVOL)

Default = 0

Function:

The individual channel volume levels are independently controlled by their respective Volume Control reg-

isters when this function is disabled. When enabled, the volume on all channels is determined by the

AOUT1 and AIN1 Volume Control register and the other Volume Control registers are ignored.

DAC_SNGVOL

DAC_SZC1

DAC_SZC0

AMUTE

MUTE ADC_SP

ADC_SNGVOL

ADC_SZC1

ADC_SZC0

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