HD64338024 datasheet(17/697 Pages) RENESAS

17 / 697 page

Rev. 7.00 Mar 10, 2005 page xvii of xlii

Item

Page

Revision (See Manual for Details)

7.1 Overview

191

Note deleted

8.2.2 Register

Configuration and

Description

Port Data Register 1

(PDR1)

196

Note amended

Note: * Pin 16 and the associated function are not

implemented on the H8/38124 Group. The register is both

readable and writeable.

Port Pull-Up Control

197

Note amended

Note: * Pin 16 and the associated function are not

implemented on the H8/38124 Group. The register is both

readable and writeable.

8.9.3 Pin Functions

Table 8.24 Port 9 Pin

Functions

232

Table amended

Pin Functions and Selection Method

P93/Vref*

VREFSEL

Pin function

P93 output pin

Vref input pin

9.2.1 Overview

246

Description amended

Timer A is an 8-bit timer with interval timing and real-time clock

time-base functions. The clock time-base function is available

when a 32.768 kHz crystal oscillator is connected as the

subclock.

• Choice of four overflow periods (1 s, 0.5 s, 0.25 s, 31.25 ms)

when timer A is used as a clock time base (using a 32.768 kHz

crystal oscillator is connected as the subclock).

9.4.3 CPU Interface

271

Description amended

When performing TCF read/write access or OCRF write access

in 16-bit mode, data will not be transferred correctly if only the

upper byte or only the lower byte is accessed. Access must be

performed for all 16 bits (using two consecutive byte-size MOV

instructions), and the upper byte must be accessed before the

lower byte.

9.5.2 Register

Descriptions

Timer Mode Register

G (TMG)

Bit 7

Bit 6

285

Table amended

Setting condition:

Set when input capture input signal is high level and TCG

overflows from H'FF to H'00

Setting condition:

Set when TCG overflows from H'FF to H'00 while input capture

input signal is high level or during interval operation

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