HD64338024 datasheet(15/697 Pages) RENESAS

15 / 697 page

Rev. 7.00 Mar 10, 2005 page xv of xlii

Item

Page

Revision (See Manual for Details)

6.5.3 Block

Configuration

Figure 6.8(1) Block

Configuration of

32-kbyte Flash

Memory

156

Figure title amended

Figure 6.8(2) Block

Configuration of

16-kbyte Flash

Memory

157

Newly added

6.6.3 Erase Block

Table 6.6 Division of

Blocks to Be Erased

162

Table amended

EBR

Bit Name

Block (Size)

Address

EB0

EB0 (1 Kbyte)

H'0000 to H'03FF

EB1

EB1 (1 Kbyte)

H'0400 to H'07FF

EB2

EB2 (1 Kbyte)

H'0800 to H'0BFF

EB3

EB3 (1 Kbyte)

H'0C00 to H'0FFF

EB4

EB4 (12 Kbytes)

H'1000 to H'3FFF (HD64F38122)

EB4 (28 Kbytes)

H'1000 to H'7FFF (HD64F38124,

HD64F38024, HD64F38024R)

6.7 On-Board

Programming Modes

164

Description amended

At reset-start in reset mode, the series of HD64F38024,

HD64F38024R, HD64F38124, and HD64F38122 changes to a

mode depending on the TEST pin settings, P95 pin settings,

and input level of each port, as shown in table 6.7.

6.7.1 Boot Mode

Table 6.9 Oscillating

Frequencies (fosc) for

which Automatic

Adjustment of LSI Bit

Rate Is Possible

166

Table amended

Product Group

Host Bit Rate

Oscillating Frequencie

s (fOSC) Range of LSI

4,800 bps

8 to 10 MHz

2,400 bps

4 to 10 MHz

F-ZTAT version of

H8/38024 Group and

F-ZTAT version of

H8/38024R Group

1,200 bps

2 to 10 MHz

19,200 bps

16 to 20 MHz

F-ZTAT version of

H8/38124 Group

9,600 bps

8 to 20 MHz

4,800 bps

6 to 20 MHz

2,400 bps

2 to 20 MHz

1,200 bps

2 to 20 MHz

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