H838024R datasheet(111/697 Pages) RENESAS

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Section 2 CPU

Rev. 7.00 Mar 10, 2005 page 69 of 652

REJ09B0042-0700

Example 2: BSET instruction executed designating port 3

P37 and P36 are designated as input pins, with a low-level signal input at P37 and a high-level

signal at P36. The remaining pins, P35 to P31, are output pins and output low-level signals. In this

example, the BSET instruction is used to change pin P30 to high-level output.

[A: Prior to executing BSET]

P37

P36

P35

P34

P33

P32

P31

P30

Input/output Input

Input

Output

Pin state

Low level High level Low level Low level Low level Low level Low level Low level

PCR3

00111111

PDR3

10000000

[B: BSET instruction executed]

BSET

@PDR3

The BSET instruction is executed designating port 3.

[C: After executing BSET]

P37

P36

P35

P34

P33

P32

P31

P30

Input/output Input

Input

Output

Pin state

Low level High level Low level Low level Low level Low level Low level High level

PCR3

00111111

PDR3

100000

[D: Explanation of how BSET operates]

When the BSET instruction is executed, first the CPU reads port 3.

Since P37 and P36 are input pins, the CPU reads the pin states (low-level and high-level input).

P35 to P30 are output pins, so the CPU reads the value in PDR3. In this example PDR3 has a value

of H'80, but the value read by the CPU is H'40.

Next, the CPU sets bit 0 of the read data to 1, changing the PDR3 data to H'41. Finally, the CPU

writes this value (H'41) to PDR3, completing execution of BSET.

As a result of this operation, bit 0 in PDR3 becomes 1, and P30 outputs a high-level signal.

However, bits 7 and 6 of PDR3 end up with different values.

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