H838024R datasheet(75/697 Pages) RENESAS

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Section 2 CPU

Rev. 7.00 Mar 10, 2005 page 33 of 652

REJ09B0042-0700

• Register indirect with post-increment—@Rn+

The @Rn+ mode is used with MOV instructions that load registers from memory.

The register field of the instruction specifies a 16-bit general register containing the address of

the operand. After the operand is accessed, the register is incremented by 1 for MOV.B or 2 for

MOV.W. For MOV.W, the original contents of the 16-bit general register must be even.

• Register indirect with pre-decrement—@–Rn

The @–Rn mode is used with MOV instructions that store register contents to memory.

The register field of the instruction specifies a 16-bit general register which is decremented by

1 or 2 to obtain the address of the operand in memory. The register retains the decremented

value. The size of the decrement is 1 for MOV.B or 2 for MOV.W. For MOV.W, the original

contents of the register must be even.

Absolute Address—@aa:8 or @aa:16: The instruction specifies the absolute address of the

operand in memory.

The absolute address may be 8 bits long (@aa:8) or 16 bits long (@aa:16). The MOV.B and bit

manipulation instructions can use 8-bit absolute addresses. The MOV.B, MOV.W, JMP, and JSR

instructions can use 16-bit absolute addresses.

For an 8-bit absolute address, the upper 8 bits are assumed to be 1 (H'FF). The address range is

H'FF00 to H'FFFF (65280 to 65535).

Immediate—#xx:8 or #xx:16: The instruction contains an 8-bit operand (#xx:8) in its second

byte, or a 16-bit operand (#xx:16) in its third and fourth bytes. Only MOV.W instructions can

contain 16-bit immediate values.

The ADDS and SUBS instructions implicitly contain the value 1 or 2 as immediate data. Some bit

manipulation instructions contain 3-bit immediate data in the second or fourth byte of the

instruction, specifying a bit number.

Program-Counter Relative—@(d:8, PC): This mode is used in the Bcc and BSR instructions.

An 8-bit displacement in byte 2 of the instruction code is sign-extended to 16 bits and added to the

program counter contents to generate a branch destination address. The possible branching range

is –126 to +128 bytes (–63 to +64 words) from the current address. The displacement should be an

even number.

Memory Indirect—@@aa:8: This mode can be used by the JMP and JSR instructions. The

second byte of the instruction code specifies an 8-bit absolute address. The word located at this

address contains the branch destination address.

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