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H838024R bảng dữ liệu(PDF) 74 Page - Renesas Technology Corp

tên linh kiện H838024R
Giải thích chi tiết về linh kiện  Renesas 8-Bit Single-Chip Microcomputer Super Low Power Series
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nhà sản xuất  RENESAS [Renesas Technology Corp]
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H838024R bảng dữ liệu(HTML) 74 Page - Renesas Technology Corp

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Section 2 CPU
Rev. 7.00 Mar 10, 2005 page 32 of 652
REJ09B0042-0700
2.4
Addressing Modes
2.4.1
Addressing Modes
The H8/300L CPU supports the eight addressing modes listed in table 2.1. Each instruction uses a
subset of these addressing modes.
Table 2.1
Addressing Modes
No.
Address Modes
Symbol
1
Register direct
Rn
2
Register indirect
@Rn
3
Register indirect with displacement
@(d:16, Rn)
4
Register indirect with post-increment
Register indirect with pre-decrement
@Rn+
@–Rn
5
Absolute address
@aa:8 or @aa:16
6
Immediate
#xx:8 or #xx:16
7
Program-counter relative
@(d:8, PC)
8
Memory indirect
@@aa:8
Register Direct—Rn: The register field of the instruction specifies an 8- or 16-bit general register
containing the operand.
Only the MOV.W, ADD.W, SUB.W, CMP.W, ADDS, SUBS, MULXU (8 bits
× 8 bits), and
DIVXU (16 bits ÷ 8 bits) instructions have 16-bit operands.
Register Indirect—@Rn: The register field of the instruction specifies a 16-bit general register
containing the address of the operand in memory.
Register Indirect with Displacement—@(d:16, Rn): The instruction has a second word (bytes 3
and 4) containing a displacement which is added to the contents of the specified general register to
obtain the operand address in memory.
This mode is used only in MOV instructions. For the MOV.W instruction, the resulting address
must be even.



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