FALXT972MCCA4 datasheet(27/92 Pages) INTEL

27 / 92 page

Intel

® LXT972M Single-Port 10/100 Mbps PHY Transceiver

Datasheet

Document Number: 302875-005

Revision Date: 27-Oct-2005

5.2.3.1.2

MDIO Frame Structure

The physical interface consists of a data line (MDIO) and clock line (MDC). The frame structure is

shown in Figure 3 and Figure 4 (Read and Write).

MDIO Interface timing is given in Chapter 7.0, “Electrical Specifications”.

5.2.3.2

Hardware Control Interface

The LXT972M Transceiver provides a Hardware Control Interface for applications where the

MDIO is not desired. The Hardware Control Interface uses the hardware configuration pins to set

device configuration. For details, see Section 5.4.4, “Hardware Configuration Settings” on

page 33.

Figure 3. Management Interface Read Frame Structure

Figure 4. Management Interface Write Frame Structure

MDC

MDIO

(Read)

32 "1"s

0110

Preamble

Op Code

PHY Address

Turn

Around

D15

D14

Data

Write

Read

D15

D14

Idle

High Z

B3489-01

MDC

MDIO

(Write)

32 "1"s

0101

Preamble

Op Code

PHY Address

Turn

Around

D15

D14

Data

Idle

Write

B3490-01

FALXT972MCCA4 bảng dữ liệu(PDF) 27 Page - Intel Corporation

FALXT972MCCA4 bảng dữ liệu(HTML) 27 Page - Intel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92

bảng dữ liệu tải về

Link URL