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FALXT972MCCA4 bảng dữ liệu(PDF) 67 Page - Intel Corporation |
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FALXT972MCCA4 bảng dữ liệu(HTML) 67 Page - Intel Corporation |
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67 / 92 page ![]() Intel ® LXT972M Single-Port 10/100 Mbps PHY Transceiver Datasheet 67 Document Number: 302875-005 Revision Date: 27-Oct-2005 Figure 24. Intel® LXT972M Transceiver 10BASE-T Receive Timing Table 32. Intel® LXT972M Transceiver 10BASE-T Receive Timing Parameter Sym Min Typ 1 Max Units 2 Test Conditions RXD, RX_DV. Setup to RX_CLK High. t1 10 – – ns – RXD, RX_DV, RX_ER Hold from RX_CLK High t2 10 – – ns – TPIP/N in to RXD out (Rx latency) t3 4.2 – 6.6 BT – CRS asserted to RXD, RX_DV, RX_ER asserted t4 5 – 32 BT – RXD, RX_DV, RX_ER de-asserted to CRS de-asserted t5 0.3 – 0.5 BT – TPI in to CRS asserted t6 2 – 28 BT – TPI quiet to CRS de-asserted t7 6 – 10 BT – TPI in to COL asserted t8 1 – 31 BT – TPI quiet to COL de-asserted t9 5 – 10 BT – 1. Typical values are at 25 °C and are for design aid only, not guaranteed, and not subject to production testing. 2. BT (Bit Time) is the duration of one bit as transferred to and from the MAC and is the reciprocal of the bit rate. 10BASE-T bit time = 10-7 s or 100 ns. RX_CLK RXD, RX_DV, RX_ER CRS TPI t3 t4 t2 t6 t1 t7 t5 COL t8 t9 B3457-01 |
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