4559 datasheet(49/148 Pages) RENESAS

49 / 148 page

Rev.1.04

Aug 23, 2007

Page 49 of 146

REJ03B0188-0104

4559 Group

RESET FUNCTION

System reset is performed by the followings:

• “L” level is applied to the RESET pin externally,

• System reset instruction (SRST) is executed,

• Reset occurs by watchdog timer,

• Reset occurs by built-in power-on reset

• Reset occurs by voltage drop detection circuit

Then when “H” level is applied to RESET pin, software starts

from address 0 in page 0.

(1) RESET pin input

System reset is performed certainly by applying “L” level to

RESET pin for 1 machine cycle or more when the following

condition is satisfied;

the value of supply voltage is the minimum value or more of the

recommended operating conditions.

Fig 48. Structure of RESET pin and its peripherals

Fig 49. RESET pin input waveform and reset release timing

Power-on reset circuit

WEF

Voltage drop detection circuit

RESET pin

(Note 2)

(Note 1)

Pull-up transistor

Internal reset signal

Watchdog reset signal

SRST instruction

Notes 1:

This symbol represents a parasitic diode.

2: Applied potential to RESET pin must be VDD or less.

0.3VDD

0.85VDD

(Note 1)

Program starts

(address 0 in page 0)

Reset input

1 machine cycle or more

RESET

f(RING)

Notes 1: Keep the value of supply voltage to the minimum value or more of the

recommended operating conditions.

2: It depends on the internal state at reset.

On-chip oscillator (internal oscillator) is counted 1376

times (Note 2).

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