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DSPIC33F bảng dữ liệu(PDF) 74 Page - Microchip Technology |
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DSPIC33F bảng dữ liệu(HTML) 74 Page - Microchip Technology |
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74 / 80 page  dsPIC33F/PIC24H PROGRAMMING SPECIFICATION DS70152D-page 74 Preliminary © 2007 Microchip Technology Inc. 8.0 AC/DC CHARACTERISTICS AND TIMING REQUIREMENTS Table 8-1 lists AC/DC characteristics and timing requirements. TABLE 8-1: AC/DC CHARACTERISTICS AND TIMING REQUIREMENTS Standard Operating Conditions Operating Temperature: –40 °C-85°C. Programming at 25°C is recommended. Param No. Symbol Characteristic Min Max Units Conditions D111 VDD Supply Voltage During Programming VDDCORE 3.60 V Normal programming(1) D112 IPP Programming Current on MCLR —5 μA D113 IDDP Supply Current During Programming — 2 mA D031 VIL Input Low Voltage VSS 0.2 VDD V D041 VIH Input High Voltage 0.8 VDD VDD V D080 VOL Output Low Voltage — 0.6 V IOL = 8.5 mA @ 3.6V D090 VOH Output High Voltage VDD – 0.7 — V IOH = -3.0 mA @ 3.6V D012 CIO Capacitive Loading on I/O pin (PGD) — 50 pF To meet AC specifications D013 CF Filter Capacitor Value on VCAP 110 μF Required for controller core P1 TPGC Serial Clock (PGC) Period 136 — ns P1A TPGCL Serial Clock (PGC) Low Time 40 — ns P1B TPGCH Serial Clock (PGC) High Time 40 — ns P2 TSET1 Input Data Setup Time to Serial Clock ↓ 15 — ns P3 THLD1 Input Data Hold Time from PGC ↓ 15 — ns P4 TDLY1 Delay between 4-bit Command and Command Operand 40 — ns P4A TDLY1A Delay between Command Operand and Next 4-bit Command 40 — ns P5 TDLY2 Delay between Last PGC ↓ of Command to First PGC ↑ of Read of Data Word 20 — ns P6 TSET2VDD ↑ Setup Time to MCLR ↑ 100 — ns P7 THLD2 Input Data Hold Time from MCLR ↑ 25 — ms P8 TDLY3 Delay between Last PGC ↓ of Command Byte to PGD ↑ by Programming Executive 12 — μs P9a TDLY4 Programming Executive Command Processing Time 10 — μs P9b TDLY5 Delay between PGD ↓ by Programming Executive to PGD Released by Programming Executive 15 23 μs P10 TDLY6 PGC Low Time After Programming 400 — ns P11 TDLY7 Bulk Erase Time 200 — ms P12 TDLY8 Page Erase Time 20 — ms P13 TDLY9 Row Programming Time 1.5 — ms P14 TR MCLR Rise Time to Enter ICSP mode — 1.0 μs P15 TVALID Data Out Valid from PGC ↑ 10 — ns P16 TDLY10 Delay between Last PGC ↓ and MCLR ↓ 0— s P17 THLD3MCLR ↓ to VDD ↓ — 100 ns Note 1: VDD must also be supplied to the AVDD pins during programming. AVDD and AVSS should always be within ±0.3V of VDD and VSS, respectively. |
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