M25PX32-VMP6F datasheet(35/63 Pages) STMICROELECTRONICS

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M25PX32

Instructions

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6.9

Read Lock Register (RDLR)

The device is first selected by driving Chip Select (S) Low. The instruction code for the Read

Lock Register (RDLR) instruction is followed by a 3-byte address (A23-A0) pointing to any

location inside the concerned sector. Each address bit is latched-in during the rising edge of

Serial Clock (C). Then the value of the Lock Register is shifted out on Serial Data output

(DQ1), each bit being shifted out, at a maximum frequency fC, during the falling edge of

Serial Clock (C).

The instruction sequence is shown in Figure 16.

The Read Lock Register (RDLR) instruction is terminated by driving Chip Select (S) High at

any time during data output.

Any Read Lock Register (RDLR) instruction, while an Erase, Program or Write cycle is in

progress, is rejected without having any effects on the cycle that is in progress.

Figure 16.

Read Lock Register (RDLR) instruction sequence and data-out sequence

Table 9.

Lock Register out(1)

Values of (b1, b0) after Power-up are defined in Section 7: Power-up and Power-down.

Bit

Bit name

Value

Function

b7-b2

Reserved

Sector Lock Down

‘1’

The Write Lock and Lock Down bits cannot be changed.

Once a ‘1’ is written to the Lock Down bit it cannot be cleared

to ‘0’, except by a power-up.

‘0’

The Write Lock and Lock Down bits can be changed by

writing new values to them.

Sector Write Lock

‘1’

Write, Program and Erase operations in this sector will not be

executed. The memory contents will not be changed.

‘0’

Write, Program and Erase operations in this sector are

executed and will modify the sector contents.

DQ0

AI13738

DQ1

3456789 10

28 29 30 31 32 33 34 35

22 21

3210

36 37 38

76543

High Impedance

Lock Register Out

Instruction

24-bit address

MSB

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