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STM8L052R8 bảng dữ liệu(PDF) 17 Page - STMicroelectronics |
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STM8L052R8 bảng dữ liệu(HTML) 17 Page - STMicroelectronics |
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17 / 109 page ![]() STM8L052R8 Functional overview Doc ID023337 Rev 2 17/109 Figure 2. High density value line STM8L05xxx clock tree diagram 1. The HSE clock source can be either an external crystal/ceramic resonator or an external source (HSE bypass). Refer to Section HSE clock in the STM8L15x and STM8L16x reference manual (RM0031). 2. The LSE clock source can be either an external crystal/ceramic resonator or a external source (LSE bypass). Refer to Section LSE clock in the STM8L15x and STM8L16x reference manual (RM0031). 3.5 Low power real-time clock The real-time clock (RTC) is an independent binary coded decimal (BCD) timer/counter. Six byte locations contain the second, minute, hour (12/24 hour), week day, date, month, year, in BCD (binary coded decimal) format. Correction for 28, 29 (leap year), 30, and 31 day months are made automatically.The subsecond field can also be read in binary format. The calendar can be corrected from 1 to 32767 RTC clock pulses. This allows to make a synchronization to a master clock. The RTC offers a digital calibration which allows an accuracy of +/-0.5ppm. It provides a programmable alarm and programmable periodic interrupts with wakeup from Halt capability. ● Periodic wakeup time using the 32.768 kHz LSE with the lowest resolution (of 61 µs) is from min. 122 µs to max. 3.9 s. With a different resolution, the wakeup time can reach 36 hours. ● Periodic alarms based on the calendar can also be generated from every second to every year. A clock security system detects a failure on LSE, and can provide an interrupt with wakeup capability. The RTC clock can automatically switch to LSI in case of LSE failure. The RTC also provides 3 anti-tamper detection pins. This detection embeds a programmable filter and can wakeup the MCU. HSE OSC 1-16 MHz HSI RC 16 MHz LSI RC 38 k Hz LSE OSC 32 768 kHz HSI LSI RTC prescaler /1;2;4;8;16;32;64 PCLK to peripherals RTCCLK/2 to LCD to IWDG SYSCLK HSE LSI LSE OSC_OUT OSC32_OUT OSC_IN OSC32_IN clock output CCO prescaler /1;2;4;8;16;32;64 HSI LSI HSE LSE CCO to core and memory SYSCLK Prescaler /1;2;4;8;16;32;64;128 IWDGCLK RTCSEL[3:0] LSE CLKBEEPSEL[1:0] to BEEP BEEPCLK MS30324V1 CSS configurable . / 2 Peripheral Clock enable (20 bits) to RTC RTCCLK c lock enable (1 bit) LCDCLK to LCD SYSCLK Halt clock enable (1 bit) LCD peripheral RTCCLK LCD peripheral CSS_LSE |
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