TDA4841 datasheet(26/60 Pages) PHILIPS

26 / 60 page

1999 Oct 25

Philips Semiconductors

Product speciﬁcation

I2C-bus autosync deﬂection controller for

PC monitors

TDA4841PS

Notes

1. For duration of vertical blanking pulse see subheading “Vertical oscillator (oscillator frequency in application without

adjustment of free-running frequency ffr(V))”.

2. Continuous blanking at CLBL (pin 16) will be activated, if one of the following conditions is true:

a) No horizontal flyback pulses at HFLB (pin 1) within a line

b) X-ray protection is triggered

c) Voltage at HPLL2 (pin 30) is low during soft start

d) Supply voltage at VCC (pin 10) is low

e) PLL1 unlocked while frequency-locked loop is in search mode.

3. Oscillator frequency is fmin when no sync input signal is present (no continuous blanking at pins 16 and 17).

4. Loading of HPLL1 (pin 26) is not allowed.

5. Voltage at HPLL1 (pin 26) is fed to HBUF (pin 27) via a buffer. Disturbances caused by horizontal sync are removed

by an internal sample-and-hold circuit.

6. All vertical and EW adjustments according note 8, but VSIZE = 80% (register VSIZE = 63, VGAIN = 63 and control

bit VOVSCN = 0).

7. Value of resistor at VREF (pin 23) may not be changed.

THRESHOLDS DERIVED FROM HPLL2 VOLTAGE

VHPLL2(blank)(ul)

upper limit for continuous

blanking

−

4.6

−

VHPLL2(bduty)(ul)

upper limit for variation of

BDRV duty cycle

−

4.0

−

VHPLL2(bduty)(ll)

lower limit for variation of BDRV

duty cycle

−

3.2

−

VHPLL2(hduty)(ul)

upper limit for variation of

HDRV duty cycle

−

3.2

−

VHPLL2(hduty)(ll)

lower limit for variation of HDRV

duty cycle

−

1.8

−

VHPLL2(stby)(ll)

lower limit for VOUT1 and

VOUT2 to be active via I2C-bus

soft start

−

1.1

−

VHPLL2(stby)(ul)

upper limit for standby voltage

−

VHPLL2(stby)(ll)

lower limit for VOUT1 and

VOUT2 to be active via external

DC current

−

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

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