ADIN1300CCPZ-R7 datasheet(85/96 Pages) AD

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Data Sheet

ADIN1300

analog.com

Rev. B | 85 of 96

This register provides the distance to the first fault on Pair 3.

Table 117. Bit Descriptions for CDIAG_FLT_DIST_3

Bits

Bit Name

Description

Reset

Access

[15:8]

RESERVED

Reserved.

0x0

[7:0]

CDIAG_FLT_DIST_3

This bit field provides the distance to the first fault on Pair 3 in meters. A value of 0xFF indicates an unknown

result.

0xFF

Cable Diagnostics Cable Length Estimate Register

Address: 0xBA25, Reset: 0x00FF, Name: CDIAG_CBL_LEN_EST

This register provides an estimate of the cable length in meters based on the signal processing and is estimated during link establishment for

100BASE-TX and 1000BASE-T.

Table 118. Bit Descriptions for CDIAG_CBL_LEN_EST

Bits

Bit Name

Description

Reset

Access

[15:8]

RESERVED

Reserved.

0x0

[7:0]

CDIAG_CBL_LEN_EST

This bit field provides a cable length estimate in meters. A value of 0xFF indicates an unknown result.

0xFF

LED Pulse Stretching Duration Register

Address: 0xBC00, Reset: 0x0011, Name: LED_PUL_STR_DUR

When the LED_PUL_STR_DUR_SEL bit field in the LED_CTRL_1 register (Address 0x001B, Bits[3:2]) is set to 2'b11, the

LED_PUL_STR_DUR register determines the LED pulse stretching duration.

Table 119. Bit Descriptions for LED_PUL_STR_DUR

Bits

Bit Name

Description

Reset

Access

[15:6]

RESERVED

Reserved.

0x0

[5:0]

LED_PUL_STR_DUR

When the LED_PUL_STR_DUR_SEL bit field in the LED_CTRL_1 register (Address 0x001B, Bits[3:2]) is set

to 2'b11, the LED_PUL_STR_DUR bit field determines the LED pulse stretching duration. Multiply the value

specified by 8 to determine the duration in milliseconds.

0x11

R/W

LED Active Low Status Register

Address: 0xBC01, Reset: 0x0000, Name: LED_A_INV_EN

When this register is set, it specifies that the LED_0 output signal is active low. Note that the PHY is capable of automatically sensing whether

the LED_0 is active high or low. Note that the default value of this register bit is configurable via the hardware configuration pins. The hardware

configuration pin allows the default operation of the PHY to be configured in unmanaged applications. The default state depends on the

hardware strapping configuration on LED_0. For Mode 1 and Mode 2, this register returns to 0, whereas for Mode 3 and Mode 4, this register

defaults to 1.

Table 120. Bit Descriptions for LED_A_INV_EN

Bits

Bit Name

Description

Reset

Access

[15:1]

RESERVED

Reserved.

0x0

LED_A_INV_EN

When this bit is set, it specifies that the LED signal is active low. Note that the default value of this register bit is

configurable via the hardware configuration pins.

0x0

R/W

SUBSYSTEM REGISTER SUMMARY

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