ADIN1300CCPZ-R7 datasheet(77/96 Pages) AD

77 / 96 page

Data Sheet

ADIN1300

analog.com

Rev. B | 77 of 96

This register specifies the length in bytes of the interframe gap to be inserted between frames by the frame generator.

Table 93. Bit Descriptions for FG_IFG_LEN

Bits

Bit Name

Description

Reset

Access

[15:8]

RESERVED

Reserved.

0x0

[7:0]

FG_IFG_LEN

Interframe gap length in bytes.

0xC

R/W

Frame Generator Number of Frames High Register

Address: 0x941C, Reset: 0x0000, Name: FG_NFRM_H

This register is Bits[31:16] of a 32-bit register that specifics the number of frames to be generated each time the frame generator is enabled or

restarted.

Table 94. Bit Descriptions for FG_NFRM_H

Bits

Bit Name

Description

Reset

Access

[15:0]

FG_NFRM_H

Bits[31:16] of the Number of Frames to be Generated.

0x0

R/W

Frame Generator Number of Frames Low Register

Address: 0x941D, Reset: 0x0100, Name: FG_NFRM_L

This register is Bits[15:0] of a 32-bit register that specifics the number of frames to be generated each time the frame generator is enabled or

restarted.

Table 95. Bit Descriptions for FG_NFRM_L

Bits

Bit Name

Description

Reset

Access

[15:0]

FG_NFRM_L

Bits[15:0] of the Number of Frames to be Generated.

0x100

R/W

Frame Generator Done Register

Address: 0x941E, Reset: 0x0000, Name: FG_DONE

This register is used to indicate that the frame generator has completed the generation of the number of frames requested in the FG_NFRM_H

Table 96. Bit Descriptions for FG_DONE

Bits

Bit Name

Description

Reset

Access

[15:1]

RESERVED

Reserved.

0x0

FG_DONE

This bit reads as 1'b1 to indicate that the generation of frames has completed. When set, this bit goes high and it latches

high until it is unlatched by reading.

0x0

FIFO_SYNC Register

Address: 0x9427, Reset: 0x0000, Name: FIFO_SYNC

When set, the transmit FIFO is configured for synchronous operation (except in 1000BASE-T slave mode) to minimize latency.

Table 97. Bit Descriptions for FIFO_SYNC

Bits

Bit Name

Description

Reset

Access

[15:1]

RESERVED

Reserved.

0x0

ADIN1300CCPZ-R7 bảng dữ liệu(PDF) 77 Page - Analog Devices

ADIN1300CCPZ-R7 bảng dữ liệu(HTML) 77 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96

bảng dữ liệu tải về

Link URL