SAA7780 datasheet(19/70 Pages) PHILIPS

19 / 70 page

ThunderBird Q3D PCI Audio

SAA7780

Accelerator

Philips Semiconductors

Product Specification

1999 Sep 30

Serial Configuration Port

Test Interface

PCLK

I-T

PCI Bus Clock Input

PCLK is the PCI bus clock input. It is used to synchronize all PCI

bus operations and typically runs at 33MHz.

RST#

PCI Bus Reset

An active low version of the system reset, this signal causes the PCI

interface to return to the idle states in all state machines and

asynchronously three-states all PCI bus signals. All registers will be

reset to their default values as well. The CODEC interface line

should be all driven inactive along with the external memory

interface. This reset will assert the DSP reset.

CFGDAT

101

I,PU-T

Serial Configuration Data

This pin is used to shift in PCI configuration data for the Subsystem

ID and the Subsystem Vendor ID in each of the PCI configuration

headers present in the SAA7780 chip. The Serial Configuration Port

is a standard I2C interface. This line should never be pulled low.

CFGCLK

102

O-T

Serial Configuration Clock

The serial clock is a 400 KHz clock generated from OSC and

supplied to an external serial EEPROM to synchronize the serial

configuration data.

TRI#

I-T

Tri-State Test Enable

When this pin is pulled low and RST# is pulsed asserted, all output

and I/O pins of the SAA7780 will be forced into a three-state

condition. Pulsed assertion of the RST# signal will release the

SAA7780 from this test mode.

NAND#

I-T

NAND Tree Test Enable

When this pin is pulled low and RST# is pulsed asserted, the

SAA7780 will enter the parametric NAND tree test mode. The

details of the NAND tree test mode are described later in this

document.

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