XRT83SL314IB datasheet(61/83 Pages) EXAR

61 / 83 page

XRT83SL314

14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT

REV. 1.0.1

LCV/OF

Line Code Violation / Counter Overflow

This bit serves a dual purpose. By default, this bit monitors the line

code violation activity. However, if bit 7 in register 0xE5h is set to a

"1", this bit monitors the overflow status of the internal LCV

counter. An interrupt will not occur unless the LCV/OFIE is set to

"1" in the channel register 0x04h and GIE is set to "1" in the global

0 = No Alarm

1 = A line code violation, bipolar violation, or excessive zeros has

occurred

NLCD

Network Loop Code Detection

The network loop code detection is always active regardless if the

interrupt generation is disabled. This bit indicates the NLCD activ-

ity. An interrupt will not occur unless the NLCDIE is set to "1" in the

channel register 0x04h and GIE is set to "1" in the global register

0xE0h.

0 = No Alarm

1 = Network loop code detected according to the mode selected in

channel register 0x03h

AISD

Alarm Indication Signal

The alarm indication signal detection is always active regardless if

the interrupt generation is disabled. This bit indicates the AIS

activity. An interrupt will not occur unless the AISIE is set to "1" in

the channel register 0x04h and GIE is set to "1" in the global regis-

ter 0xE0h.

0 = No Alarm

1 = An all ones signal is detected

RLOS

Receiver Loss of Signal

The receiver loss of signal detection is always active regardless if

the interrupt generation is disabled. This bit indicates the RLOS

activity. An interrupt will not occur unless the RLOSIE is set to "1"

in the channel register 0x04h and GIE is set to "1" in the global

0 = No Alarm

1 = An RLOS condition is present

QRPD

Quasi Random Pattern Detection

The quasi random pattern detection is always active regardless if

the interrupt generation is disabled. This bit indicates that a QRPD

has been detected. An interrupt will not occur unless the QRPDIE

is set to "1" in the channel register 0x04h and GIE is set to "1" in

the global register 0xE0h.

0 = No Alarm

1 = A QRP is detected

NOTE: The GIE bit in the global register 0xE0h must be set to "1" in addition to the individual register bits to enable the

interrupt pin.

TABLE 30: MICROPROCESSOR REGISTER 0X05H BIT DESCRIPTION

CHANNEL 0-13 (0X05H-0XD5H)

BIT

NAME

FUNCTION

Type

Default

Value

(HW reset)

XRT83SL314IB bảng dữ liệu(PDF) 61 Page - Exar Corporation

XRT83SL314IB bảng dữ liệu(HTML) 61 Page - Exar Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83

bảng dữ liệu tải về

Link URL