XRT83SL314IB datasheet(18/83 Pages) EXAR

18 / 83 page

XRT83SL314

REV. 1.0.1

14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT

FIGURE 2. SIMPLIFIED BLOCK DIAGRAM OF THE CLOCK SYNTHESIZER

1.1

ALL T1/E1 Mode

To reduce system noise and power consumption, the XRT83SL314 offers an ALL T1/E1 mode. Since most

line card designs are configured to operate in T1 or E1 only, the LIU can be selected to shut off the timing

references for the mode not being used by programming the appropriate global register. By default the ALL

T1/E1 mode is enabled (ALLT1/E1 bit = "0"). If the LIU is configured for T1, all E1 clock references and the

8kHz reference are shut off internally to the chip. This reduces the amount of internal clocks switching within

the LIU, hence reducing noise and power consumption. In E1 mode, the T1 clock references are internally

shut off, however the 8kHz reference is available. To disable this feature, the ALLT1/E1 bit must be set to a "1"

in the appropriate global register.

2.0

RECEIVE PATH LINE INTERFACE

The receive path of the XRT83SL314 LIU consists of 14 independent T1/E1/J1 receivers.

The following

section describes the complete receive path from RTIP/RRING inputs to RCLK/RPOS/RNEG outputs.

simplified block diagram of the receive path is shown in Figure 3.

FIGURE 3. SIMPLIFIED BLOCK DIAGRAM OF THE RECEIVE PATH

Clock

Synthesizer

Internal

Reference

1.544MHz

2.048MHz

Input Clock

8kHz

1.544Mhz

2.048MHz

2.048/4.096/8.192/16.384 MHz

1.544/3.088/6.176/12.352MHz

8kHzOUT

MCLKE1out

MCLKT1out

MCLKT1Nout

MCLKE1Nout

Programmable

HDB3/B8ZS

Decoder

Rx Jitter

Attenuator

Clock & Data

Recovery

Peak Detector

& Slicer

Rx Equalizer

Control

RTIP

RRING

RCLK

RNEG

RPOS

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