MPC5553_07 datasheet(10/66 Pages) FREESCALE

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MPC5553 Microcontroller Data Sheet, Rev. 2.0

Electrical Characteristics

Freescale Semiconductor

3.6

Voltage Regulator Controller (VRC) and

Power-On Reset (POR) Electrical Specifications

Table 6. VRC/POR Electrical Specifications

Spec

Characteristic

Symbol

Min

Max

Units

1.5 V (VDD) POR negated (ramp up)

1.5 V (VDD) POR asserted (ramp down)

V_POR15

1.1

1.35

3.3 V (VDDSYN) POR negated (ramp up)

3.3 V (VDDSYN) POR asserted (ramp down)

V_POR33

2.0

2.85

RESET pin supply (VDDEH6) POR negated (ramp up)

RESET pin supply (VDDEH6) POR asserted (ramp down)

1 V

IL_S (Table 9, Spec15) is guaranteed to scale with VDDEH6 down to V_POR5.

V_POR5

2.0

2.85

4VRC33 voltage before the regulator controller allows the pass

transistor to start turning on

V_TRANS_START

1.0

2.0

5VRC33 voltage when the regulator controller allows the pass

transistor to completely turn on2, 3

2 Supply full operating current for the 1.5 V supply when the 3.3 V supply reaches this range.

3 It is possible to reach the current limit during ramp up—do not treat this event as short circuit current.

V_TRANS_ON

2.0

2.85

6VRC33 voltage greater than the voltage at which the VRC

keeps the 1.5 V supply in regulation4, 5

4 At peak current for device.

5 Requires compliance with Freescale’s recommended board requirements and transistor recommendations. Board signal

traces/routing from the VRCCTL package signal to the base of the external pass transistor and between the emitter of the

pass transistor to the VDD package signals must have a maximum of 100 nH inductance and minimal resistance

(less than 1

Ω). V

RCCTL must have a nominal 1 μF phase compensation capacitor to ground. VDD must have a 20 μF

(nominal) bulk capacitor (greater than 4

μF over all conditions, including lifetime). Place high-frequency bypass capacitors

consisting of eight 0.01

μF, two 0.1 μF, and one 1 μF capacitors around the package on the V

DD supply signals.

V_VRC33REG

3.0

—

Current can be sourced by VRCCTL

I_VRCCTL

6 I_VRCCTL is measured at the following conditions: V

DD = 1.35 V, VRC33 = 3.1 V, V_VRCCTL = 2.2 V.

– 40o C

11.0

—

25o C

9.0

—

150o C (Tj)

7.5

—

Voltage differential during power up such that:

VDD33 can lag VDDSYN or VDDEH6, before VDDSYN and

VDDEH6 reach the V_POR33 and V_POR5 minimums

respectively.

VDD33_LAG

—

1.0

Absolute value of slew rate on power supply pins

—

V/ms

Required gain:

IDD / I_VRCCTL (@VDD = 1.35 V, fsys = fMAX)

5, 7

7 Values are based on IDD from high-use applications as explained in the IDD Electrical Specification.

BETA8

8 BETA is measured on a per-part basis and is calculated as (IDD

÷ I_VRCCTL), and represents the worst-case external

transistor BETA.

– 40o C

55.09

——

25o C

58.09

——

150o C (Tj)

70.09

500

—

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